THCV215 and THCV216
V-by-One
®
HS High-speed Video Data Transmitter and Receiver
General Description
THCV215 and THCV216 are designed to support
video data transmission between the host and
display.
The chipset can transmit 39bit video data and 3bit
sync data via only a single differential cable at an
LVDS clock frequency from 20MHz to 100MHz.
The chipset, which has two high-speed data lanes,
can transmit the video data up to 1080p/10b/60Hz,
1080p/12b/60Hz. The maximum serial data rate is
3.75Gbps/lane.
Color
Depth
6bit
8bit
10bit
12bit
Link
Single/Dual
Single/Dual
Single/Dual
Single/Dual
LVDS
Clock Frequency
20MHz to 100MHz
20MHz to 100MHz
20MHz to 85MHz
20MHz to 75MHz
Features
Color depth selectable: 6/8/10/12 bit
Single/Dual Link selectable
AC coupling
LVDS Input internal termination
CORE 1.8V, LVDS 3.3V
Package: 64 pin TSSOP
Wide frequency range
CDR requires no external frequency reference
Supports Spread Spectrum Clocking: Up to
30kHz/0.5%(center spread)
V-by-One
®
HS standard Version1.4 compliant
Block Diagram
THCV215
TLA0+/-
・
・
・
TLF0+/-
TLCLK0+/-
TLA1+/-
・
・
・
TLF1+/-
TLCLK1+/-
THCV216
Deserializer
LVDS
Serializer
TX0+ RX0+
TX0- RX0-
・
・
・
RLA0+/-
・
・
・
RLF0+/-
RLCLK0+/-
RLA1+/-
・
・
・
RLF1+/-
RLCLK1+/-
LVDS
Deserializer
・
・
・
Serializer
LVDS
Deserializer
Deserializer
Serializer
LVDS
Serializer
PLL
・
・
・
TX1+ RX1+
TX1- RX1-
Deskew & Formatter
Formatter
・
・
・
Color depth
(6/8/10/12)
Single/Dual
Pre-emphasis
PDN
CDR
PLL
Controls
HTPDN
LOCKN
Controls
Color depth
(6/8/10/12)
Single/Dual
RS
PDN
THCV215-216_Rev.2.70_E
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Contents Page
General Description ................................................................................................................................................. 1
Features .................................................................................................................................................................... 1
Block Diagram ......................................................................................................................................................... 1
Pin Diagram ............................................................................................................................................................. 3
Pin Description......................................................................................................................................................... 4
Functional Description ............................................................................................................................................ 5
Absolute Maximum Ratings0F ............................................................................................................................. 13
Operating Conditions ............................................................................................................................................ 13
Electrical Specifications ........................................................................................................................................ 14
AC Timing Diagrams and Test Circuits ............................................................................................................... 17
Package ................................................................................................................................................................... 24
Notices and Requests ............................................................................................................................................. 25
THCV215-216_Rev.2.70_E
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Pin Diagram
LAGND
LAVDH
TLA0-
TLA0+
TLB0-
TLB0+
TLC0-
TLC0+
TLCLK0-
TLCLK0+
TLD0-
TLD0+
TLE0-
TLE0+
TLF0-
TLF0+
TLA1-
TLA1+
TLB1-
TLB1+
TLC1-
TLC1+
TLCLK1-
TLCLK1+
TLD1-
TLD1+
TLE1-
TLE1+
TLF1-
TLF1+
LAVDH
LAGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LPVDL
LPGND
SDSEL
COL1
COL0
RDY
PDN
HTPDN
LOCKN
VDL
GND
CAVDL
CAGND
TX0-
TX0+
CAGND
TX1-
TX1+
CAGND
CAVDL
CPGND
CPVDL
DRV1
DRV0
PRE1
PRE0
Reserved0
Reserved1
GND
VDL
LPGND
LPVDL
LPVDH
LPGND
SDSEL
COL1
COL0
HTPDN
LOCKN
VDL
GND
CPVDL0
CPGND0
CAVDL
CAGND
RX0-
RX0+
CAGND
CAGND
RX1-
RX1+
CAGND
CAVDL
CPGND1
CPVDL1
GND
VDL
Reserved1
PDN
Reserved2
Reserved3
RS
LPGND
LPVDH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LAGND
LAVDH
RLA0-
RLA0+
RLB0-
RLB0+
RLC0-
RLC0+
RLCLK0-
RLCLK0+
RLD0-
RLD0+
RLE0-
RLE0+
RLF0-
RLF0+
RLA1-
RLA1+
RLB1-
RLB1+
RLC1-
RLC1+
RLCLK1-
RLCLK1+
RLD1-
RLD1+
RLE1-
RLE1+
RLF1-
RLF1+
LAVDH
LAGND
THCV215
64pin
TSSOP
THCV216
64pin
TSSOP
THCV215-216_Rev.2.70_E
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Pin Description
THCV215
Pin Name Pin #
TX0 +/-
50,51
TX1 +/-
47,48
TLA0+/-
4,3
TLB0+/-
6,5
TLC0+/-
8,7
TLCLK0+/- 10,9
TLD0+/-
12,11
TLE0+/-
14,13
TLF0+/-
16,15
TLA1+/-
18,17
TLB1+/-
20,19
TLC1+/-
22,21
TLCLK1+/- 24,23
TLD1+/-
26,25
TLE1+/-
28,27
TLF1+/-
30,29
LOCKN
56
HTPDN
57
Type*
CO
CO
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI
LI
I
I
Description
CML Data Output
THCV216
Pin Name Pin #
Type* Description
RX0 +/-
15,14
CI
RX1 +/-
19,18
CI CML Data Input
RLA0+/-
61,62
LO
RLB0+/-
59,60
LO
RLC0+/-
57,58
LO
RLCLK0+/ 55,56
LO
RLD0+/-
53,54
LO
RLE0+/-
51,52
LO
RLF0+/-
49,50
LO
RLA1+/-
47,48
LO
RLB1+/-
45,46
LO
RLC1+/-
43,44
LO
RLCLK1+/ 41,42
LO
RLD1+/-
39,40
LO
RLE1+/-
37,38
LO
RLF1+/-
35,36
LO LVDS Data Output
LOCKN
7
O Lock detect output (open drain)
HTPDN
6
O Hot plug detect output (open drain)
Power down input
H: Normal Operation
L: Power down (High-Z)
Color depth select input
L,L: 6bit
L,H: 8bit
H,L: 10bit
H,H: 12bit
Single/Dual select input
L: Channel0 enable, Channel1 disable
H: Channel0, Channel1 enable
PDN
58
I
COL1,
COL0
SDSEL
DRV1
DRV0
61,60
62
42
41
I
I
I
I
LVDS Data Input
Lock detect input
Hot plug detect input
Power down input
H: Normal Operation
L: Power down (CML output High Fix,
other High-Z)
Color depth select input
L,L: 6bit
L,H: 8bit
H,L: 10bit
H,H: 12bit
Single/Dual select input
L: Channel0 enable, Channel1 disable
H: Channel0, Channel1 enable
Must be tied to GND
Must be tied to VDL
Pre-emphasis level select input
L,L: 0%
H,L: 100%
L,H: not available
H,H: not available
Link status ready output
L: not ready
H: ready
Field BET mode enable input
L: Normal operation (default)
H: Field BET mode enabled
Must be tied to GND
1.8V power supply pin for digital circuitry
Ground pin for digital circuitry
1.8V power supply pin for CML output
Ground pin for CML output
1.8V power supply pin for PLL circuitry
Ground pin for PLL circuitry
1.8V power supply pin for LVDS PLL
Ground pin for LVDS PLL circuitry
3.3V power supply pin for LVDS input
Ground pin for LVDS input
PDN
27
I
COL1,
COL0
SDSEL
4,5
3
I
I
RS
30
PRE1,
PRE0
RDY
Reserved1
Reserved0
VDL
GND
CAVDL
CAGND
CPVDL
CPGND
LPVDL
LPGND
LAVDH
LAGND
40,39
59
37
38
35,55
36,54
45,53
46,49,52
43
44
33,64
34,63
2,31
1,32
I
O
I
I
P
P
P
P
P
P
P
P
P
P
Direction of RS pin depends on
Reserved3.
LVDS swing range select input
IO3 when Reserved3=L
H: Normal swing (350mV typ.)
L: Reduced swing (200mV typ.)
Field BET output when Reserved3=H.
Goes LOW when errors detected.
I
I
P
P
P
Must be tied to GND
Field BET mode enable input
L: Normal operation (default)
H: Field BET mode enabled
1.8V power supply pin for digital circuitry
Ground pin for digital circuitry
1.8V power supply pin for CML input
Reserved
1,2
Reserved3
VDL
GND
CAVDL
26,28
29
8,25
9,24
12,21
13,16,
17,20
10
11
23
22
1,32
2,31
34,63
33,64
Note) All CMOS inputs are 1.8V-inputs
except for THCV216's RS
CAGND
P Ground pin for CML input
CPVDL0
P 1.8V power supply pin for PLL circuitry
CPGND0
P Ground pin for PLL circuitry
CPVDL1
P 1.8V power supply pin for PLL circuitry
CPGND1
P Ground pin for PLL circuitry
LPVDH
P 3.3V power supply pin for LVDS PLL
LPGND
P Ground pin for LVDS PLL circuitry
LAVDH
P 3.3V power supply pin for LVDS output
LAGND
P Ground pin for LVDS output
*type symbol
I=1.8V CMOS Input, O=1.8V CMOS Output, IO3=3.3V CMOS I/O
LI=LVDS Input, LO= LVDS Output
CI=CML Input, CO=CML Output
P=Power
THCV215-216_Rev.2.70_E
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Functional Description
Functional Overview
With V-by-One
®
HS’s proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV215
and THCV216 enable transmission of 18/24/30/36bits per pixel video data (Rn/Gn/Bn/CONTn), Hsync
(HSYNCn), Vsync (VSYNCn) data and Data Enable (DE) by single/dual differential pair cable with minimal
external components.
THCV215, the transmitter, inputs LVDS data (including video data, Hsync, Vsync and DE) and serializes video
data and Hsync, Vsync data separately, depending on the polarity of DE. DE is a signal which indicates whether
video or Hsync, Vsync data are active. When DE is high, it serializes video data inputs into a single differential
data stream. And it transmits serialized Hsync, Vsync data when DE is low.
THCV216, the receiver, automatically extracts the clock from the incoming data stream and converts the serial
data into video data with DE being high or Hsync, Vsync data with DE being low, recognizing which type of
serial data is being sent by the transmitter. And it outputs the recovered data in the form of LVDS data.
THCV216 can seamlessly operate for a wide range of a serial bit rate from 600Mbps to 3.75Gbps/channel,
detecting the frequency of an incoming data stream, and recovering both the clock and data by itself.
It does not need any external frequency reference, such as a crystal oscillator.
Data Enable Requirement (DE)
There are some requirements for DE as described in Figure 2, Figure 3 and Table 15.
Dual LVDS input to THCV215 should be synchronized in terms of DE transition. See Figure 2.
If DE=Low, Hsync and Vsync data of same cycle are transmitted. Otherwise video data of that are transmitted
(DE=High). SYNC data from receiver in DE=High period are previous data of DE transition. See Figure 3.
The length of DE being low and high is at least 2 clock cycles long as described in Table 15.
Data Enable must be toggled like High -> Low -> High at regular interval.
THCV215
Rn/Gn/Bn
CONTn
D[39:0]
THCV216
H
D[39:0]
Rn/Gn/Bn
CONTn
H
HSYNCn
VSYNCn
Hsync
Vsync
L
L
Hsync
Vsync
HSYNCn
VSYNCn
DE
DE
Figure 1. Conceptual diagram of the basic operation of the chipset
Vdiff = (TLCLK0+)
–
(TLCLK0-)
DE
Vdiff = (TLC0+)
–
(TLC0-)
DE
DE
DE
DE
DE
Vdiff = (TLCLK1+)
–
(TLCLK1-)
DE
Vdiff = (TLC1+)
–
(TLC1-)
DE
DE
DE
DE
DE
Figure 2. Service condition of DE input synchronization
THCV215-216_Rev.2.70_E
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