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TC7SET32FU,LJ(CT

Description
IC GATE OR 1CH 2-INP USV
Categorylogic    logic   
File Size127KB,7 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
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TC7SET32FU,LJ(CT Overview

IC GATE OR 1CH 2-INP USV

TC7SET32FU,LJ(CT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
MakerToshiba Semiconductor
package instructionTSSOP,
Reach Compliance Codeunknown
Factory Lead Time12 weeks
seriesAHCT/VHCT/VT
JESD-30 codeR-PDSO-G5
length2 mm
Logic integrated circuit typeOR GATE
Number of functions1
Number of entries2
Number of terminals5
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)11.5 ns
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width1.25 mm
TC7SET32FU
CMOS Digital Integrated Circuits Silicon Monolithic
TC7SET32FU
1. Functional Description
2-Input OR Gate
2. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
AEC-Q100 (Rev. H) (Note 1)
Wide operating temperature range: T
opr
= -40 to 125
(Note 2)
High speed operation: t
pd
= 4.2 ns (typ.) (V
CC
= 5.0 V, C
L
= 15 pF)
Low power dissipation: I
CC
= 2.0
µA
(max) (T
a
= 25
)
Compatible with TTL outputs: V
IL
= 0.8 V (max)
V
IH
= 2.0 V (min)
5.5 V tolerant inputs
Balanced Propagation Delay: t
PLH
t
PHL
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
Note 2: For devices with the ordering part number ending in J(CT. T
opr
= -40 to 85
for the other devices.
3. Packaging
USV
Start of commercial production
©2016 Toshiba Corporation
1
1996-09
2017-05-16
Rev.3.0

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