SL23EP09
Not Recommended for New Designs
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
10 to 220 MHz operating frequency range
Low output clock skew: 45ps-typ
Low output clock jitter:
50 ps-typ cycle-to-cycle jitter
20 ps-typ period jitter
Low part-to-part output skew: 90 ps-typ
Wide 2.5 V to 3.3 V power supply range
Low power dissipation:
26 mA-max at 66 MHz and VDD=3.3 V
24 mA-max at 66 MHz and VDD=2.5V
One input drives 9 outputs organized as 4+4+1
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Digital Embeded Systems
Description
The SL23EP09 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9) clock
outputs from one (1) reference input clock, for high speed
clock distribution applications.
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from the
CLKOUT pin.
The SL23EP09 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs are
needed, four (4) bank-B output clock buffers can be tri-stated
to reduce power dissipation and jitter. The select inputs can
also be used to tri-state both banks A and B or drive them
directly from the input bypassing the PLL and making the
product behave like a Non-Zero Delay Buffer (NZDB).
The high-drive version operates up to 220MHz and 200MHz
at 3.3V and 2.5V power supplies respectively.
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Applications
Benefits
Up to nine (9) distribution of input clock
Standard and High-Dirive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
Block Diagram
Low Power and
Low Jitter
PLL
MUX
CLKOUT
CLKIN
CLKA1
CLKA2
CLKA3
S2
CLKA4
S1
Input Selection
Decoding Logic
CLKB1
CLKB2
CLKB3
2
2
CLKB4
VDD
GND
Rev 2.0, May 12, 2008
Page 1 of 14
2400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL23EP09
Pin Configuration
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CLKA1
2
3
5
6
7
8
15
14
13
12
11
10
9
CLKA2
CLKA4
CLKA3
VDD
GND
VDD
4
GND
CLKB1
CLKB2
CLKB4
CLKB3
S1
S2
16-Pin SOIC and TSSOP
CLKIN
1
16
CLKOUT
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
9
Pin Name
Pin Type
Input
Pin Description
CLKIN
Reference Frequency Clock Input. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
3.3V or 2.5V Power Supply.
Power Ground.
CLKA1
CLKA2
VDD
GND
Output
Output
Power
Power
CLKB1
CLKB2
S2
S1
Output
Output
Input
Input
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Select Input, select pin S2. Weak pull-up (250kΩ).
Select Input, select pin S1. Weak pull-up (250kΩ).
10
11
12
13
14
15
16
CLKB3
CLKB4
GND
VDD
Output
Output
Power
Power
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Power Ground.
3.3V or 2.5V Power Supply.
CLKA3
CLKA4
Output
Output
Output
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
CLKOUT
Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250kΩ).
Rev 2.0, May 12, 2008
Page 2 of 14
SL23EP09
General Description
The SL23EP09 is a low skew, low jitter Zero Delay Buffer
with very low operating current.
The product includes an on-chip high performance PLL that
locks into the input reference clock and produces nine (9)
output clock drivers tracking the input reference clock for
systems requiring clock distribution.
in addition to CLKOUT that is used for internal PLL
feedback, there are two (2) banks with four (4) outputs in
each bank, bringing the number of total available output
clocks to nine (9).
Input and output Frequency Range
The input and output frequency range is the same. But, it
depends on VDD and drive levels as given in the below
Table 1.
Select Input Control
The SL23EP09 provides two (2) input select control pins
called S1 and S2. This feature enables users to selects
various states of output clock banks-A and bank-B, output
source and PLL shutdown features as shown in the Table 2.
The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kΩ weak
pull-up resistors to VDD.
PLL Bypass Mode
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VDD(V)
3.3
3.3
2.5
2.5
If the S2 and S1 pins are logic High(1) and Low(0)
respectively, the on-chip PLL is shutdown and bypassed,
and all the nine output clocks bank A, bank B and CLKOUT
clocks are driven directly from the reference input clock. In
this operation mode SL23EP09 works like a non-ZDB fanout
buffer.
High and Low-Drive Product Options
Drive
STD
STD
Min(MHz)
10
10
10
10
Max(MHz)
220
200
180
167
HIGH
HIGH
The SL23EP09 is offered with High-Drive “-1H” and
Standard-Drive “-1” options. These drive options enable the
users to control load levels, frequency range and EMI
control. Refer to the AC electrical tables for the details.
Skew and Zero Delay
Table 1. Input/Output Frequency Range
If the input clock frequency is DC (GND to VDD), this is
detected by an input frequency detection circuitry and all
nine (9) clock outputs are forced to Hi-Z. The PLL is
shutdown to save power. In this shutdown state, the product
draws less than 12 μA supply current.
SpreadThru
™
Feature
All outputs should drive the similar load to achieve output-to-
output skew and input-to-output specifications given in the
AC electrical tables. However, Zero delay between input
and outputs can be adjusted by changing the loading of
CLKOUT relative to the banks A and B clocks since
CLKOUT is the feedback to the PLL.
Power Supply Range (VDD)
If a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL23EP09 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from its
reference input to the output clocks. The same spread
characteristics at the input are passed through the PLL and
drivers without any degradation in spread percent (%),
spread profile and modulation frequency
The SL23EP09 is designed to operate in a wide power
supply range from 2.3V (Min) to 3.6V (Max). An internal on-
chip voltage regulator is used to supply PLL constant power
supply of 1.8V, leading to a consistent and stable PLL
electrical performance in terms of skew, jitter and power
dissipation. Contact SLI for 1.8V power supply version ZDB
called SL23EPL09.
Rev 2.0, May 12, 2008
Page 3 of 14
SL23EP09
S2
0
0
1
1
S1
0
1
0
1
Clock A1-A4
Tri-state
Driven
Driven
Driven
Clock B1-4
Tri-state
Tri-state
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Status
On
On
Off
On
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Table 2. Select Input Decoding
1500
CLKIN Input to CLKA or CLKB Delay (ps)
1000
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FBK Load – CLKA or CLKB Load (pF)
Figure 1. CLKIN Input to CLK A and B Delay
(In terms of load difference between CLKOUT and CLK A and B)
Rev 2.0, May 12, 2008
Page 4 of 14
SL23EP09
Absolute Maximum Ratings
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
In operation, C-Grade
In operation, I-Grade
No power is applied
Condition
Min.
– 0.5
– 0.5
0
– 40
– 65
–
–
Max.
4.6
VDD+0.5
70
85
Unit
V
V
°C
°C
°C
°C
°C
V
V
V
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150
125
260
In operation, power is applied
JEDECCC22-A114D
Soldering Temperature
ESD Rating (Human Body Model)
ESD Rating (Machine Model)
-4000
-1500
-200
4000
1500
200
ESD Rating (Change Device Model)
JEDECCC22-C101C
JEDECCC22-A115D
Rev 2.0, May 12, 2008
Page 5 of 14
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