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WP33C2A1EFEI-450B2

Description
WP3 2C2A1 450MHZ,LF BALLS,PBFBUM
Categorysemiconductor    The embedded processor and controller   
File Size740KB,2 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
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WP33C2A1EFEI-450B2 Overview

WP3 2C2A1 450MHZ,LF BALLS,PBFBUM

WP3 WinPath3
Next Generation Access Systems
Packet Processor
Released Product Brief
Product Overview
The WinPath3, with its enhanced carrier-grade software, is the third
generation of WinPath products. Building on hundreds of successful
communications systems deployments, the WinPath3 extends PMC’s
proven formula of complete protocol solutions to a significantly
higher level of performance.
The WinPath3 integrates control plane and enhanced data plane
processing components. Control plane processing is based on two
high-performance MIPS 34K multi-threaded processors. Data plane
processing uses new hardware accelerators for packet classification,
hierarchical shaping, additional security standards and more to off-
load common processing tasks. The accelerators are flexibly
combined with a field-proven, fully-programmable, high-perfor-
mance multi-threaded multi-core data path processor subsystem. 12
cores are available (up from 6 in the WinPath2) and operating speed
has increased.
The WinPath3 leverages a broad set of supplied protocols developed
for WinPath1 and WinPath2, including support for L2 and L3 termi-
nation (Ethernet, ML-PPP, IMA, CES), PWE3 (Ethernet, TDM, HDLC,
ATM), Packet Network Synchronization (IEEE 1588v2, Synchronous
Ethernet, adaptive and differential clock recovery), interworking
(MPLS, IPv4/IPv6 Routing, VLAN-aware bridging), OAM (Ethernet,
ATM), QoS (policing, shaping, per-flow queuing, WRED) and more.
Product Highlights
Third generation family of communication processors provided with
carrier-class IP protocol and interworking software
5x performance, higher integration than 2nd-generation WinPath2
Extensive set of interfaces supports IP up to 10 GbE and TDM/SDH
up to OC-48 unchannelized or channelized (via companion
UFE412/448 device)
System bus interfaces include PCIe, integrated SERDES
Highly flexible integrated DDR and Flash memory controllers
Powerful multi-threaded, multi-core acceleration with RAM-based
code store supports evolving standards in Wireline (Carrier
Ethernet, Enterprise Access, Mobile Backhaul, GPON, DSLAM) and
Wireless (LTE, WiMAX, Fixed Wireless Access) systems
Data path software is royalty-free and carrier-class supported with
a C-language API for rapid system integration for over 60 protocols
Available data path software supports networking at Layer 2 and
above, interworking, QoS, and protocols such as MPLS, MPLS-TP,
PB, PBB, EFM G.Bond, PWE3-SATOP, Link Aggregation, GRE,
WRED, WFQ, VLAN-aware bridging and many others
Rich suite of development tools and source code licensing options
supports customer-specific requirements
Benefits
Enhanced interfaces with on-chip SERDES and the latest memory
interfaces for lowered BOM costs and simple system integration
Straightforward upgrade of WinPath2 applications for improved
performance and capability of next-generation access systems
Minimum design risk, short time-to-market, and lowered costs for
new or migrated systems
Production-hardened protocols supplied royalty-free
LTE Access and Transport protocols and WiMAX, which generally
require significant OEM and deployment customization, fully
supported by royalty-free source licensing
Block Diagram
14 Lane SERDES Mux
PCIe
WinComm
System
Functions
UART
8x WinNet
I2C
CFU
Debug/Boot/
Management
Mgmt ENET
Timers
512K
L2
Cache
Con-
troller
Classifier
Parser
Fabric
Policer
2x SPi3 32 bit
3x SPi3 8 bit
3x UL2/3x PL2
EMPHY
UTOPIA L2/3
POS L2
SPI.3
EMPHY
Pin Mux
3x UPI
SRAM
12x WinGines
16x SGMII or
8x 2.5SGMII
8x RMII
12x RGMII
72x SS-SMII
2x 10GbE
XAUI
PCIe
SGMII or
2.5SGMII
GMII
RGMII
SMII
SS-SMII
MIPS 34K
64K I- / 32K D-
L1 Cache
Controller
MIPS 34K
64K I- / 32K D-
L1 Cache
Controller
Shaper
Security
16 TDI
Serial
DDR 2/3
32 Bits
DDR 2/3
32 Bits
DDR 2/3
32 Bits
Timing/
Synch
T1/E1
CT Bus
H-MVIP
Flash/
Peripheral
Bus
Async I/F
Control Path
Data Path
App Bus/Packet Bus/
Parameter Bus (Optional)
PMC-2110882, Issue 2
Copyright © 2012 PMC-Sierra, Inc.
All rights reserved. Proprietary and Confidential to PMC-Sierra and for its customers’ internal use.

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