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LTC2142IUP-12#TRPBF

Description
IC ADC DUAL 12BIT 65MSPS 64QFN
CategoryAnalog mixed-signal IC    converter   
File Size1MB,38 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Environmental Compliance
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LTC2142IUP-12#TRPBF Overview

IC ADC DUAL 12BIT 65MSPS 64QFN

LTC2142IUP-12#TRPBF Parametric

Parameter NameAttribute value
Brand NameLinear Technology
Is it Rohs certified?conform to
MakerLinear ( ADI )
Parts packaging codeQFN
package instructionHVQCCN, LCC64,.35SQ,20
Contacts64
Manufacturer packaging codeUP
Reach Compliance Codecompliant
ECCN code3A991.C.2
Maximum analog input voltage1.25 V
Minimum analog input voltage0.7 V
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N64
JESD-609 codee3
length9 mm
Maximum linear error (EL)0.022%
Humidity sensitivity level1
Number of analog input channels2
Number of digits12
Number of functions1
Number of terminals64
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output bit codeOFFSET BINARY, 2\'S COMPLEMENT BINARY
Output formatPARALLEL, WORD
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC64,.35SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.8 V
Certification statusNot Qualified
Sampling rate65 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width9 mm
LTC2142-12/
LTC2141-12/LTC2140-12
12-Bit, 65Msps/
40Msps/25Msps Low Power
Dual ADCs
DESCRIPTION
The LTC
®
2142-12/LTC2141-12/LTC2140-12 are 2-channel
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.8dB SNR and
89dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.08ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.3LSB
RMS
.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
n
2-Channel Simultaneously Sampling ADC
70.8dB SNR
89dB SFDR
Low Power: 92mW/65mW/48mW Total
46mW/33mW/24mW per Channel
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
Selectable Input Ranges: 1V
P-P
to 2V
P-P
750MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
64-Pin (9mm
×
9mm) QFN Package
APPLICATIONS
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
TYPICAL APPLICATION
1.8V
V
DD
1.8V
OV
DD
2-Tone FFT, f
IN
= 70MHz and 69MHz
0
–10
–20
AMPLITUDE (dBFS)
CH 1
ANALOG
INPUT
S/H
12-BIT
ADC CORE
D1_11
CMOS,
DDR CMOS
OR
DDR LVDS
OUTPUTS
–30
–40
–50
–60
–70
–80
D1_0
D2_11
CH 2
ANALOG
INPUT
S/H
12-BIT
ADC CORE
OUTPUT
DRIVERS
D2_0
–90
–100
–110
–120
65MHz
CLOCK
CLOCK
CONTROL
21421012 TA01a
0
20
10
FREQUENCY (MHz)
30
21821012
TA01b
GND
OGND
21421012fa
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