UPD44324095F5-E33-EQ2 datasheet, PDF

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UPD44324095F5-E33-EQ2: Description36M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION; File Size308KB，32 Pages; ManufacturerNEC ( Renesas ); Websitehttps://www2.renesas.cn/zh-cn/

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UPD44324095F5-E33-EQ2 Overview

36M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD44324085, 44324095, 44324185, 44324365

36M-BIT DDRII SRAM SEPARATE I/O

2-WORD BURST OPERATION

Description

The

PD44324085 is a 4,194,304-word by 8-bit, the

PD44324095 is a 4,194,304-word by 9-bit, the

PD44324185 is a

2,097,152-word by 18-bit and the

PD44324365 is a 1,048,576-word by 36-bit synchronous double data rate static RAM

fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD44324085,

PD44324095,

PD44324185 and

PD44324365 integrate unique synchronous peripheral circuitry

and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K

and /K.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

•

1.8 ± 0.1 V power supply and HSTL I/O

•

DLL circuitry for wide output data valid window and future frequency scaling

•

Separate independent read and write data ports

•

DDR read or write operation initiated each cycle

•

Pipelined double data rate operation

•

Separate data input/output bus

•

Two-tick burst for low DDR transaction size

•

Two input clocks (K and /K) for precise DDR timing at clock rising edges only

•

Two output clocks (C and /C) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability with

s restart

•

User programmable impedance output

•

Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

•

Simple control logic for easy depth expansion

•

JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M16782EJ1V0DS00 (1st edition)

Date Published October 2004 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2003

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