UPD44164085F5-E60-EQ1 datasheet, PDF

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UPD44164085F5-E60-EQ1: Description18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION; File Size334KB，32 Pages; ManufacturerNEC ( Renesas ); Websitehttps://www2.renesas.cn/zh-cn/

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UPD44164085F5-E60-EQ1 Overview

18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD44164085, 44164185, 44164365

18M-BIT DDRII SRAM SEPARATE I/O

2-WORD BURST OPERATION

Description

The

PD44164085 is a 2,097,152-word by 8-bit, the

PD44164185 is a 1,048,576-word by 18-bit and the

PD44164365 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS

technology using full CMOS six-transistor memory cell.

The

PD44164085,

PD44164185 and

PD44164365 integrates unique synchronous peripheral circuitry and a

burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and

/K.

These products are suitable for application which require synchronous operation, high speed, low voltage, high

density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

•

1.8 ± 0.1 V power supply and HSTL I/O

•

DLL circuitry for wide output data valid window and future frequency scaling

•

Separate independent read and write data ports

•

DDR read or write operation initiated each cycle

•

Pipelined double data rate operation

•

Separate data input/output bus

•

Two-tick burst for low DDR transaction size

•

Two input clocks (K and /K) for precise DDR timing at clock rising edges only

•

Two output clocks (C and /C) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability with

s restart

•

User programmable impedance output

•

Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)

•

Simple control logic for easy depth expansion

•

JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M15823EJ7V1DS00 (7th edition)

Date Published

July

2004 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2001

UPD44164085F5-E60-EQ1 Related Products

	UPD44164085F5-E60-EQ1	UPD44164365F5-E60-EQ1	UPD44164365F5-E50-EQ1	UPD44164085	UPD44164185F5-E60-EQ1	UPD44164185F5-E50-EQ1	UPD44164185F5-E40-EQ1	UPD44164085F5-E50-EQ1	UPD44164085F5-E40-EQ1
Description	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION	18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION

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