DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD44164085, 44164185, 44164365
18M-BIT DDRII SRAM SEPARATE I/O
2-WORD BURST OPERATION
Description
The
µ
PD44164085 is a 2,097,152-word by 8-bit, the
µ
PD44164185 is a 1,048,576-word by 18-bit and the
µ
PD44164365 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The
µ
PD44164085,
µ
PD44164185 and
µ
PD44164365 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
•
1.8 ± 0.1 V power supply and HSTL I/O
•
DLL circuitry for wide output data valid window and future frequency scaling
•
Separate independent read and write data ports
•
DDR read or write operation initiated each cycle
•
Pipelined double data rate operation
•
Separate data input/output bus
•
Two-tick burst for low DDR transaction size
•
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
•
Two output clocks (C and /C) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability with
µ
s restart
•
User programmable impedance output
•
Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)
•
Simple control logic for easy depth expansion
•
JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15823EJ7V1DS00 (7th edition)
Date Published
July
2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2001
µ
PD44164085, 44164185, 44164365
Pin Configurations
/××× indicates active low signal.
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
µ
PD44164085F5-EQ1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DD
Q
NC
NC
D6
NC
NC
Q7
A
4
R, /W
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
/NW1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
/K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
/C
7
NC
/NW0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
/LD
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
A
D0 to D7
Q0 to Q7
/LD
R, /W
/NW0, /NW1
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs
: Data outputs
: Synchronous load
: Read Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remark
Refer to
Package Drawing
for the index mark.
Data Sheet M15823EJ7V1DS
3
µ
PD44164085, 44164185, 44164365
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
µ
PD44164185F5-EQ1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
NC
D9
D10
Q10
Q11
D12
Q13
V
DD
Q
D14
Q14
D15
D16
Q16
Q17
A
4
R, /W
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
/BW1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
/K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
/C
7
NC
/BW0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
/LD
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
D0 to D17
Q0 to Q17
/LD
R, /W
/BW0, /BW1
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs
: Data outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remark
Refer to
Package Drawing
for the index mark.
4
Data Sheet M15823EJ7V1DS
µ
PD44164085, 44164185, 44164365
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
µ
PD44164365F5-EQ1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
Q27
D27
D28
Q29
Q30
D30
/DLL
D31
Q32
Q33
D33
D34
Q35
TDO
2
V
SS
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
NC
D18
D19
Q19
Q20
D21
Q22
V
DD
Q
D23
Q23
D24
D25
Q25
Q26
A
4
R, /W
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
/BW2
/BW3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
/K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
/C
7
/BW1
/BW0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
/LD
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
NC
D17
D16
Q16
Q15
D14
Q13
V
DD
Q
D12
Q12
D11
D10
Q10
Q9
A
10
V
SS
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
D0 to D35
Q0 to Q35
/LD
R, /W
/BW0 to /BW3
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs
: Data outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remark
Refer to
Package Drawing
for the index mark.
Data Sheet M15823EJ7V1DS
5
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