U6264B
Standard 8K x 8 SRAM
Features
!
8192 x 8 bit static CMOS RAM
!
70 ns Access Times
!
Common data inputs and
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Description
The U6264B is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word read will
be available at the outputs DQ0 -
DQ7. After the address change, the
data outputs go High-Z until the
new read information is available.
The data outputs have no preferred
state. If the memory is driven by
CMOS levels in the active state,
and if there is no change of the
address, data input and control
signals W or G, the operating cur-
rent (at I
O
= 0 mA) drops to the
value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150
µA
typ.
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outputs
Three-state outputs
Typ. operating supply current
70 ns: 10 mA
Standby current:
< 2
µA
at T
a
≤
70 °C
Data retention current at 2 V:
< 1
µA
at T
a
≤
70 °C
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges:
0 to 70
°C
-40 to 85
°C
-40 to 125 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: PDIP28 (600 mil)
SOP28 (330 mil)
Pin Configuration
Pin Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
Signal Name
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
PDIP
22
SOP
21
20
19
18
17
16
15
Top View
April 20, 2004
1
U6264B
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
C-Type
K-Type
A-Type
C/K-Type
A-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
Min.
-0.3
-0.3
-0.3
-
0
-40
-40
-55
-65
Max.
7
V
CC
+ 0.5
b
V
CC
+ 0.5
b
1
70
85
125
125
150
100
Unit
V
V
V
W
°C
°C
°C
°C
°C
mA
Storage Temperature
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
c
a
T
stg
| I
OS
|
b
c
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
Maximum voltage is 7 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Operating Conditions
Power Supply Voltage
Data Retention Voltage
Input Low Voltage
d
Input High Voltage
d
Symbol
V
CC
V
CC(DR)
V
IL
V
IH
Conditions
Min.
4.5
2.0
-0.3
2.2
Max.
5.5
Unit
V
V
0.8
V
CC
+ 0.3
V
V
-2 V at Pulse Width 10 ns
April 20, 2004
3
U6264B
Switching Characteristics
Alt.
Time to Output in Low-Z
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address Change
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
LZ
t
WC
t
RC
t
ACE
t
OE
t
AA
t
WP
t
CW
t
AS
t
CW
t
WP
t
DS
t
DH
t
AH
t
OH
t
HZCE
t
HZWE
t
HZOE
Symbol
IEC
t
t(QX)
t
cW
t
cR
t
a(E)
t
a(G)
t
a(A)
t
w(W)
t
w(E)
t
su(A)
t
su(E)
t
su(W)
t
su(D)
t
h(D)
t
h(A)
t
v(A)
t
dis(E)
t
dis(W)
t
dis(G)
Min.
5
70
70
-
-
-
50
65
0
65
50
35
0
0
5
0
0
0
25
30
25
70
40
70
Max.
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Mode E1-Controlled
4.5 V
V
CC(DR)
≥
2 V
2.2 V
t
DR
0V
Data Retention
t
rec
2.2 V
E1
0V
V
CC
Data Retention Mode E2-Controlled
V
CC
V
CC(DR)
≥
2 V
t
DR
0.8 V
Data Retention
V
E2(DR)
≤
0.2 V
t
rec
0.8 V
E2
4.5 V
V
E2(DR)
≥
V
CC(DR)
- 0.2 V or V
E2(DR)
≤
0.2 V
V
CC(DR)
- 0.2 V
≤
V
E1(DR)
≤
V
CC(DR)
+ 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time
t
DR
:
t
rec
:
min 0 ns
min t
cR
April 20, 2004
5
DSP and ARM Processors
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