PRELIMINARY INFORMATION
ICS1726-11
Low EMI Clock Generator
Description
The ICS1726-11 generates a low EMI output clock
from a clock or crystal input. The part is designed to
dither the LCD interface clock for PDAs, printers,
scanners, modems, copiers, and others. Using ICS’
proprietary mix of analog and digital Phase-Locked
Loop (PLL) technology, the device spreads the
frequency spectrum of the output, reducing the
frequency amplitude peaks by several dB. The
ICS1726-11 offers both centered and down spread
from a high-speed clock input.
ICS offers many other clocks for computers and
computer peripherals. Consult us when you need to
remove crystals and oscillators from your board.
Features
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Packaged in 8-pin SOIC/TSSOP
Provides a spread spectrum output clock
Supports flat panel controllers
Accepts a clock or crystal input (provides same
frequency dithered output)
Input frequency range of 16 to 32 MHz
Output frequency range of 16 to 32 MHz
Center and down spread
Peak reduction by 8 dB to 16 dB typical on 3rd
through 19th odd harmonics
Low EMI feature can be disabled
Includes power down
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Block Diagram
VDD
S1:0
2
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
SSCLK
X1/CLK
Clock Buffer/
Crystal
Ocsillator
X2
External caps required for with crystal
for accurate tuning of the clock
X1
GND
MDS 1726-11 A
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 092905
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS1726-11
Low EMI Clock Generator
Pin Assignment
X1/ICLK
GND
S1
S0
1
2
3
4
8
7
6
5
X2
VDD
NC
SSCLK
Spread Direction and Percentage
Select Table
S1
Pin 3
S0
Pin 4
Spread
Direction
Spread
Percentage
8 pin (150 mil) SOIC
8-pin (173 mil) TSSOP
0
0
0
M
M
M
1
1
1
0
M
1
0
M
1
0
M
1
Center
Center
Center
Center
No Spread
Down
Down
Down
Down
±1.4
±1.1
±0.6
±0.5
-
-1.6
-2.0
-0.7
-3.0
0 = connect to GND
M = unconnected (floating)
1 = connect directly to VDD
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
X1/ICLK
GND
S1
S0
SSCLK
NC
VDD
X2
Input
Power
Input
Input
Output
—
Power
XO
Connect to a 16 to 32 MHz crystal or clock.
Connect to ground.
Function select 1 input. Selects spread amount and direction per table above.
(default-internal mid-level).
Function select 0 input. Selects spread amount and direction per table above.
(default-internal mid-level).
Clock output with Spread spectrum.
No connect. Do not connect this pin to anything.
Connect to +3.3 V.
Crystal connection to a 16 to 32 MHz crystal. Leave unconnected for clock.
MDS 1726-11 A
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 092905
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS1726-11
Low EMI Clock Generator
External Components
The ICS1726-11 requires a minimum number of
external components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 7 and 2, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS1726-11. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. So,
for a crystal with a 16 pF load capacitance, two 20 pF
[(16-6) x 2] capacitors should be used.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50Ω trace (a commonly used
trace impedance) place a 33Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
Tri-level Select Pin Operation
The S1, S0 select pins are tri-level, meaning they have
three separate states to make the selections shown in
the table on page 2. To select the M (mid) level, the
connection to these pins must be eliminated by either
floating them, or tri-stating the driver connected to the
select pin.
Spread Spectrum Profile
The ICS1726-11 low EMI clock generator uses an
optimized frequency slew rate to facilitate down stream
tracking by zero delay buffers and other PLL devices.
The frequency modulation amplitude is constant
despite variations of the input frequency.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
Modulation Rate
Frequency
Time
MDS 1726-11 A
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 092905
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS1726-11
Low EMI Clock Generator
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS1726-11. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70°C
-65 to +150°C
125°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
3.6
Units
°C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V,
Ambient Temperature 0 to +70°C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
IDD
Conditions
No load, at 3.3 V,
Fin=24 MHz
No load, at 3.3 V,
Fin=32 MHz
Min.
3.0
Typ.
3.3
23
Max.
3.6
30
35
Units
V
mA
mA
V
V
V
V
V
Input High Voltage
Input middle Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
V
IH
V
IHM
V
IL
V
OH
V
OH
V
OL
C
IN1
C
IN2
CMOS, I
OH
= -4 mA
I
OH
= -6 mA
I
OL
= -4 mA
I
OL
= -10 mA
S0, S1, pins
X1, X2 pins
0.85VDD
0.4VDD
0.0
2.4
2.0
VDD
0.5VDD
0.0
VDD
0.6VDD
0.15VDD
0.4
1.2
4
6
6
9
V
V
pF
pF
MDS 1726-11 A
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 092905
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS1726-11
Low EMI Clock Generator
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V,
Ambient Temperature 0 to +70° C
Parameter
Input Clock Frequency
Output Clock Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle to cycle Jitter
Output Rise Time
Output Fall Time
EMI Peak Frequency Reduction
Symbol
Conditions
Min.
16
16
Typ.
Max. Units
32
32
60
MHz
MHz
%
%
ps
ns
ns
dB
Time above VDD/2
Time above 1.5 V
Fin=27 MHz,
Fout=27 MHz
t
R
t
F
0.4 to 2.4 V
2.4 to 0.4 V
40
45
50
200
2.4
2.4
3.2
3.2
8 to 16
55
450
4.0
4.0
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
150
140
120
40
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
MDS 1726-11 A
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 092905
tel (408) 297-1201
●
www.icst.com
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