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SY10EP51VZITR

Description
5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK
Categorylogic    logic   
File Size569KB,8 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

SY10EP51VZITR Overview

5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK

SY10EP51VZITR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrochip
Parts packaging codeSOIC
package instructionPLASTIC, SOIC-8
Contacts8
Reach Compliance Code_compli
Other featuresNECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
series10E
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.93 mm
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su3000000000 Hz
Humidity sensitivity level1
Number of digits1
Number of functions1
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)240
power supply-5.2 V
Maximum supply current (ICC)40 mA
Prop。Delay @ Nom-Su0.42 ns
propagation delay (tpd)0.37 ns
Certification statusNot Qualified
Maximum seat height1.73 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width3.94 mm
minfmax3000 MHz
Micrel, Inc.
5V/3.3V D FLIP-FLOP WITH RESET
AND DIFFERENTIAL CLOCK
ECL Pro
®
SY10EP51V
ECL Pro
®
SY10EP51V
FEATURES
3.3V and 5V power supply options
320ps typical propagation delay
Maximum frequency > 3GHz typical
75K
internal input pulldown resistor
Transistor count: 143
ECL Pro
®
DESCRIPTION
The SY10EP51V is a D flip-flop with reset and
differential clock. The device is pin and functionally
equivalent to the EL51 device.
The reset input is an asynchronous, level triggered
signal. Data enters the master portion of the flip-flop
when CLK is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the CLK.
The differential clock inputs of the EP51V allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to
maintain stability under open input conditions. When left
open, the CLK input will be pulled down to V
EE
and the
/CLK input will be biased a V
CC
/2.
Available in 8-Pin (3mmx3mm) MSOP, SOIC and
MLF
®
(2mmx2mm) packages
PIN NAMES
Pin
CLK, /CLK
RESET
D
Q, /Q
V
CC
V
EE
Function
ECL Clock Inputs
ECL Asynchronous Reset
ECL Data Input
ECL Data Outputs
Positive Supply
Negative, 0 Supply
TRUTH TABLE
D
L
H
X
RESET
L
L
H
CLK
Z
Z
X
Q
L
H
L
Z = LOW to HIGH Transition
ECL Pro is a registered trademark of Micrel, Inc.
M9999-060409
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /0
1
Issue Date: June 2009

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