Changes to Endnote 3 ...................................................................... 4
Changes to Pin Configuration Section .......................................... 8
Changes to Evaluating the AD7679’s Performance Section...... 25
Changes to Ordering Guide .......................................................... 26
7/03—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD7679
SPECIFICATIONS
–40°C to +85°C, V
REF
= 4.096 V, AVDD = DVDD= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
Input Impedance
1
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
Zero Error, T
MIN
to T
MAX
Zero Error Temperature Drift
Gain Error, T
MIN
to T
MAX 3
Gain Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
Conditions
Min
18
–V
REF
–0.1
68
25
Typ
Max
Unit
Bits
V
V
dB
μA
V
IN+
– V
IN–
V
IN+
, V
IN–
to AGND
f
IN
= 100 kHz
570 kSPS Throughput
+V
REF
AVDD+0.1
0
–2.5
–1
18
V
REF
= 5 V
–40
–0.048
AVDD = 5 V ± 5%
f
IN
= 2 kHz, V
REF
= 5 V
V
REF
= 4.096 V
f
IN
= 10 kHz, V
REF
= 4.096 V
f
IN
= 100 kHz, V
REF
= 4.096 V
V
IN+
= V
IN–
= V
REF
/2 = 2.5 V
f
IN
= 2 kHz
f
IN
= 10 kHz
f
IN
= 100 kHz
f
IN
= 2 kHz
f
IN
= 10 kHz
f
IN
= 100 kHz
f
IN
= 2 kHz, V
REF
= 4.096 V
f
IN
= 2 kHz, –60 dB Input
±0.5
See Note 3
±1.6
±4
101
99
98
97
103
120
118
105
–115
–113
–98
98
40
26
2
5
Full-Scale Step
0.7
1.75
570
+2.5
+1.75
μs
kSPS
LSB
2
LSB
Bits
LSB
LSB
ppm/°C
% of FSR
ppm/°C
LSB
dB
4
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
ns
ps rms
ns
ns
V
V
V
μA
μA
+40
+0.048
97.5
Dynamic Range
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
–3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery
REFERENCE
External Reference Voltage Range
REF Voltage with Reference Buffer
Reference Buffer Input Voltage Range
REFBUFIN Input Current
REF Current Drain
250
250
3
4.05
1.8
–1
4.096
4.096
2.5
235
AVDD + 0.1
4.15
2.6
+1
REF
REFBUFIN = 2.5 V
REFBUFIN
570 kSPS Throughput
Rev. A | Page 3 of 28
AD7679
Parameter
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
5
Pipeline Delay
6
V
OL
V
OH
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
Operating Current
AVDD
DVDD
8
OVDD
8
POWER DISSIPATION
8
Conditions
Min
Typ
Max
Unit
–0.3
2.0
–1
–1
+0.8
DVDD + 0.3
+1
+1
V
V
μA
μA
ISINK = 1.6 mA
ISOURCE = –500 μA
0.4
OVDD – 0.6
V
V
4.75
4.75
2.7
500 kSPS Throughput
PDBUF High
5
5
5.25
5.25
DVDD + 0.3
7
V
V
V
mA
mA
μA
mW
μW
mW
°C
PDBUF High @ 500 kSPS
PDBUF High @ 1 kSPS
PDBUF Low @ 500 kSPS
TMIN to TMAX
–40
10.8
4.5
50
76
150
89
90
103
+85
TEMPERATURE RANGE
Specified Performance
1
2
9
See Analog Inputs section.
LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 μV.
3
See Definition of Specifications section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal
value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.
4
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.
5
Parallel or Serial 18-Bit.
6
Conversion results are available immediately after completed conversion.
7
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8
Tested in Parallel Reading mode.
9
Contact factory for extended temperature range.
Rev. A | Page 4 of 28
AD7679
TIMING SPECIFICATIONS
–40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 3.
Parameter
Refer to Figure 32 and Figure 33
Convert Pulsewidth
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
Refer to Figure 34, Figure 35, and Figure 36 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
Refer to Figure 38 and Figure 39 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
2
Internal SCLK Period
2
Internal SCLK HIGH
2
Internal SCLK LOW
2
SDOUT Valid Setup Time
2
SDOUT Valid Hold Time
2
SCLK Last Edge to SYNC Delay
2
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
2
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 40 and Figure 41 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
1
2
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
Min
10
1.75
Typ
Max
Unit
ns
μs
ns
μs
ns
ns
μs
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
35
1.5
2
10
1.5
250
10
1.5
20
5
45
15
10
10
10
525
3
25
12
7
4
2
3
40
10
10
10
See Table 4
1.5
25
5
3
5
5
25
10
10
18
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode.
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