DATA SHEET
Freescale Semiconductor
Technical Data
Clock Generator for PowerQUICC
III
MPC9855
Rev 4, 09/2005
MPC9855
Clock Generator for PowerQUICC III
The MPC9855 is a PLL based clock generator specifically designed for
Freescale Microprocessor and Microcontroller applications including the
PowerPC and PowerQUICC. This device generates a microprocessor input
clock. The microprocessor clock is selectable in output frequency to any of the
commonly used microprocessor input and bus frequencies. The device offers
eight low skew clock outputs in two banks, each configurable to support different
clock frequencies. The extended temperature range of the MPC9855 supports
telecommunication and networking requirements.
Features
•
•
•
•
•
•
•
•
•
•
•
8 LVCMOS outputs for processor and other circuitry
Crystal oscillator or external reference input
25 or 33 MHz Input reference frequency
Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,
50, 33, or 16 MHz
Buffered reference clock output (2 copies)
Low cycle-to-cycle and period jitter
100-lead PBGA package
100-lead Pb-free Package Available
3.3 V supply with 3.3 V or 2.5 V LVCMOS output supplies
Supports computing, networking, telecommunications applications
Ambient temperature range –40°C to +85°C
MICROPROCESSOR
CLOCK GENERATOR
SCALE 2 1
VF SUFFIX
VM SUFFIX (PB-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
Functional Description
The MPC9855 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency
is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers,
divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111,
100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor
or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also
buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired.
The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a
25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and
selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal
oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are
required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input
frequency.
The MPC9855 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.
IDT™
Clock Generator for PowerQUICC III
MPC9855
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
1
MPC9855
Clock Generator for PowerQUICC III
NETCOM
CLK
PCLK
PCLK
CLK_SEL
XTAL_IN
XTAL_OUT
XTAL_SEL
0
1
0
Ref
1
PLL
OSC
2000 MHz
1
÷N
0
QA1
QA2
QA3
÷N
QB0
QB1
QB2
QB3
QA0
PLL_BYPASS
REF_33 MHz
CLK_A[0:5]
CLK_B[0:5]
REF_OUT0
MR
REF_OUT1
REF_OUT1_E
Figure 1. MPC9855 Logic Diagram
MPC9855
IDT™
Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
2
2
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
MPC9855
Clock Generator for PowerQUICC III
NETCOM
Table 1. Pin Configurations
Pin
CLK
PCLK,
PCLK
QA0, QA1,
QA2, QA3
QB0, QB1,
QB2, QB3
REF_OUT0
REF_OUT1
XTAL_IN
XTAL_OUT
CLK_SEL
XTAL_SEL
REF_33 MHz
REF_OUT1_E
MR
PLL_BYPASS
CLK_A[0:5]
(1)
CLK_B[0:5]
(2)
V
DD
V
DDA
V
DDOA
V
DDOB
GND
I/O
Input
Input
Output
Output
Output
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
—
—
—
—
—
Type
Function
Supply
V
DD
V
DD
V
DDOA
V
DDOB
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
—
—
—
—
—
—
—
—
—
—
—
High
High
High
High
Low
High
—
—
—
—
—
—
—
Active/State
LVCMOS PLL Reference Clock Input (pull-down)
LVPECL
PLL reference clock input
(PCLK — pull-down,
PCLK
— pull-up and pull-down)
LVCMOS Clock Outputs
LVCMOS Clock Outputs
LVCMOS Reference Output (25 MHz or 33 MHz)
LVCMOS Crystal Oscillator Input Pin
LVCMOS Crystal Oscillator Output Pin
LVCMOS Select between CLK and PCLK input (pull-down)
LVCMOS Select between External Input and Crystal Oscillator Input
(pull-down)
LVCMOS Selects 33MHz input (pull-down)
LVCMOS Enables REF_OUT1 output (pull-down)
LVCMOS Master Reset (pull-up)
LVCMOS Select PLL or static test mode (pull-down)
LVCMOS Configures Bank A clock output frequency (pull-up)
LVCMOS Configures Bank B clock output frequency (pull-up)
—
—
—
—
—
3.3 V Supply
Analog Supply
Output Supply — Bank A
Output Supply — Bank B
Ground
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
Table 2. Function Table
Control
CLK_SEL
XTAL_SEL
PLL_BYPASS
REF_OUT1_E
REF_33 MHz
MR
Default
0
0
0
0
0
1
0
CLK
CLKx
Normal
Disables REF_OUT1
Selects 25 MHz Reference
Reset
1
PCLK
XTAL
Bypass
Enables REF_OUT1
Selects 33 MHz Reference
Normal
CLK_A and CLK_B control output frequencies. See
Table 3
for specific device configuration
IDT™
Clock Generator for PowerQUICC III
MPC9855
MPC9855
3
Advanced Clock Drivers Devices
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Freescale Semiconductor
3
MPC9855
Clock Generator for PowerQUICC III
NETCOM
Table 3. Output Configurations (Banks A & B)
CLK_x[0:5]
(1)
111111
111100
101000
011110
010100
001111
001100
001010
001001
001000
000111
000110
000101
000100
CLK_x[0]
(msb)
1
1
1
0
0
0
0
0
0
0
0
0
0
0
CLK_x[1]
1
1
0
1
1
0
0
0
0
0
0
0
0
0
CLK_x[2]
1
1
1
1
0
1
1
1
1
1
0
0
0
0
CLK_x[3]
1
1
0
1
1
1
1
0
0
0
1
1
1
1
CLK_x[4]
1
0
0
1
0
1
0
1
0
0
1
1
0
0
CLK_x[5]
(lsb)
1
0
0
0
0
1
0
0
1
0
1
0
1
0
N
126
120
80
60
40
30
24
20
18
16
15
12
10
8
(2)
Frequency
(MHz)
15.87
16.67
25.00
33.33
50.00
66.67
83.33
100.00
111.11
125.00
133.33
166.67
200.00
250
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
2. Minimum value for N
MPC9855
IDT™
Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
4
4
MPC9855
Advanced Clock Drivers Devices
Freescale Semiconductor
MPC9855
Clock Generator for PowerQUICC III
NETCOM
OPERATION INFORMATION
Output Frequency Configuration
The MPC9855 was designed to provide the commonly
used frequencies in PowerQUICC, PowerPC and other
microprocessor systems.
Table 3
lists the configuration
values that will generate those common frequencies. The
MPC9855 can generate numerous other frequencies that
may be useful in specific applications. The output frequency
(f
out
) of either Bank A or Bank B may be calculated by the
following equation.
f
out
= 2000 / N
where f
out
is in MHz and N = 2 * CLK_x[0:5]
This calculation is valid for all values of N from 8 to 126.
Note that N = 15 is a modified case of the configuration inputs
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
00111 or 7.
Crystal Input Operation
TBD
Power-Up and MR Operation
Figure 2
defines the release time and the minimum pulse
length for MR pin. The MR release time is based upon the
power supply being stable and within V
DD
specifications. See
Table 9
for actual parameter values. The MPC9855 may be
configured after release of reset and the outputs will be stable
for use after lock is obtained.
V
DD
MR
t
reset_rel
t
reset_pulse
Figure 2. MR Operation
Power Supply Bypassing
The MPC9855 is a mixed analog/digital product. The
architecture of the MPC9855 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all V
DD
pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
Power Consumption Calculation
For unloaded outputs the power consumption of the
MPC9855 can be calculated as follows.
P = V
DD
* I
DDBASE
+ n
A
* (V
DDOA
** 2 * C
PD
* f
A
)
+ n
B
* (V
DDOB
** 2 * C
PD
* f
B
)
where
V
DD
= core supply voltage
I
DDBASE
= base supply current
n
A
= number of A bank outputs (= 4)
n
B
= number of B bank outputs (= 4)
V
DDOA
= voltage supply on bank A outputs
V
DDOB
= voltage supply on bank B outputs
C
PD
= power dissipation capacitance
f
A
= frequency of bank A outputs
f
B
= frequency of bank B outputs
V
DD
22
µF
15
Ω
0.1
µF
V
DD
MPC9855
V
DDA
0.1
µF
Figure 3. V
CC
Power Supply Bypass
IDT™
Clock Generator for PowerQUICC III
MPC9855
MPC9855
5
Advanced Clock Drivers Devices
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Freescale Semiconductor
5
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