Si51211 Data Sheet
Three Output Factory Programmable Clock Generator
The factory programmable Si51211 is a low power, small footprint and frequency flexible
programmable clock generator targeting low power, low cost and high volume consumer
and embedded applications. The device operates from a single crystal or an external
clock source and generates 1 to 3 outputs up to 170 MHz. The device is factory pro-
grammed to provide customized output frequencies and control input such as frequency
select, spread spectrum on, power down and output enable. Center spread spectrum
can also be programmed to reduce EMI to meet board level system requirements.
Applications
• Crystal/XO replacement
• EMI reduction
• Portable devices
• Digital still camera
• IP phone
• Smart meter
KEY FEATURES
• Generates up to 3 CMOS clock outputs
from 3 to 170 MHz
• Accepts crystal or reference clock input
• 3 to 165 MHz reference clock input
• 8 to 48 MHz crystal input
• Programmable FSEL, SSONb, PD, and OE
input functions
XIN/
3
CLKIN
PLL with
Modulation
Control
Buffers,
Dividers,
and
Switch
Matrix
4
SSCLK1/
REFCLK/
OE/FSEL/
SSONb
XOUT 2
VDDO 8
VDD 1
To Pin 7
V-REG
To Core
Programmable
Configuration
Register
SSCLK2/
6 OE/SSONb/PD
To Pin 4 and Pin 6
VSS 5
7
SSCLK3
(VDDO)
silabs.com
| Smart. Connected. Energy-friendly.
Rev. 1.0
Si51211 Data Sheet
Feature List
1. Feature List
The Si51211 highlighted features are listed below.
• Generates up to 3 CMOS clock outputs from 3 to 170 MHz
• Accepts crystal or reference clock input
• 3 to 165 MHz reference clock input
• 8 to 48 MHz crystal input
• Programmable FSEL, SSONb, PD, and OE input functions
• Low power dissipation
• Separate voltage supply pins
• V
DD
= 2.5 to 3.3 V
• V
DDO
= 1.8 to 3.3 V (V
DDO
< V
DD
)
• ±0.25%, ±0.5% or ±1% spread spectrum (center spread)
• Low cycle-cycle jitter
• Ultra small 8-pin TDFN package (1.4 mm x 1.6 mm)
silabs.com
| Smart. Connected. Energy-friendly.
Rev. 1.0 | 1
Si51211 Data Sheet
Design Considerations
2. Design Considerations
2.1 Typical Application Schematic
2.2 Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1 μF must be used between VDD and VSS on pins 1 and 8. Place the capacitor on
the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept
as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. In addition, a 10 µF capacitor should be
placed between VDD and VSS.
Series Termination Resistor:
A series termination resistor is recommended if the distance between the outputs (SSCLK or REFCLK
pins) and the load is over 1 ½ inches. The nominal impedance of the SSCLK output is about 30 Ω. Use a 20 Ω resistor in series with the
output to terminate a 50 Ω trace impedance and place a 20 Ω resistor as close to the SSCLK output as possible.
Crystal and Crystal Load:
Only use a parallel resonant fundamental AT cut crystal. Do not use higher overtone crystals. To meet the
crystal initial accuracy specification (in ppm) make sure that the external crystal load capacitor is matched to the crystal load specifica-
tion. To determine the value of CL1 and CL2, use the following formula:
CL1 = CL2 = 2CL − (Cpin + Cp);
where CL is the load capacitance stated by the crystal manufacturer,
Cpin is the Si51211 pin capacitance (3 pF), and
Cp is the parasitic capacitance of the PCB traces.
Example:
If a crystal with CL = 12 pF specification is used and Cp = 1 pF (parasitic PCB capacitance on PCB), 19 or 20 pF external
capacitors from pins XIN (pin 2) and XOUT (Pin 3) to VSS are required. Users must verify Cp value.
Table 2.1. Crystal Specifications
Equivalent Series Resistance (ESR)
< 50 Ω
Crystal Output Capacitance (CO)
< 3 pF
Load Capacitance (CL)
< 13 pF
silabs.com
| Smart. Connected. Energy-friendly.
Rev. 1.0 | 2
Si51211 Data Sheet
Electrical Specifications
3. Electrical Specifications
Table 3.1. DC Electrical Specifications
(V
DD
= 2.5 V ±10%, or V
DD
= 3.3V ±-10%, V
DDO
= V
DD
, C
L
= 10 pF, T
A
= –40 to 85 °C)
Parameter
Operating Voltage
Symbol
V
DD
Test Condition
V
DD
= 3.3 V ± 10%
V
DD
= 2.5 V ± 10%
V
DDO
Output High Voltage
V
OH
V
DDO
< V
DD
I
OH
= –4 mA,
V
DDX
= V
DD
or V
DDO
Output Low Voltage
Input High Voltage
Input Low Voltage
Operating Supply Current
1
V
OL
V
IH
V
IL
I
DD
I
OL
= 4 mA
CMOS Level
CMOS Level
F
IN
= 12 MHz, SSCLK1 = 12 MHz,
SSCLK2 = 24 MHz, C
L
= 5 pF, V
DD
= V
DDO
= 3.3 V
IDD
PD
Z
O
R
PUP
/R
PD
C
IN
C
L
Pin 6
Input pin capacitance
Min
2.97
2.25
1.71
V
DDX
–
0.5
—
0.7 V
DD
0
—
Typ
3.3
2.5
—
—
Max
3.63
2.75
3.6
—
Unit
V
V
V
V
—
—
—
6.3
0.3
—
0.3 V
DD
10
V
V
V
mA
Power Down Current
Nominal Output Impedance
Internal Pull-up/Pull-down Resistor
Input Pin Capacitance
Load Capacitance
Note:
1. I
DD
depends on input and output frequency configurations.
—
—
—
—
—
0.5
30
150k
3
—
0.65
—
—
5
10
mA
Ω
Ω
pF
pF
Table 3.2. AC Electrical Specifications
(V
DD
= 2.5 V ±10%, or V
DD
= 3.3 V ±10%, V
DDO
= V
DD
, C
L
= 10 pF, T
A
= –40 to 85 °C)
Parameter
Input Frequency Range
Input Frequency Range
Output Frequency Range
Frequency Accuracy
Output Duty Cycle
Symbol
F
IN1
F
IN2
F
OUT
F
ACC
DC
OUT
Condition
Crystal input
Reference clock Input
SSCLK1/2/3
Configuration dependent
Measured at V
DDO
/2
F
OUT
< 75 MHz
Measured at V
DDO
/2
F
OUT
> 75 MHz
Input Duty Cycle
DC
IN
CLKIN, CLKOUT through PLL
30
50
70
%
40
50
60
%
Min
8
3
3
—
45
Typ
—
—
—
0
50
Max
48
165
170
—
55
Unit
MHz
MHz
MHz
ppm
%
silabs.com
| Smart. Connected. Energy-friendly.
Rev. 1.0 | 3
Si51211 Data Sheet
Electrical Specifications
Parameter
Output Rise/Fall Time
Period Jitter
Symbol
t
r
/t
f
PJ
1
PJ
2
Cycle-to-Cycle Jitter
CCJ
1
CCJ
2
Power-up Time
Output Enable Time
t
PU
t
OE
Condition
C
L
= 10 pF, 20 to 80%
SSCLK1/2/3, at the same frequen-
cy
SSCLK1/2/3, at different output fre-
quencies
1
SSCLK1/2/3, at the same frequen-
cy
SSCLK1/2/3, at different output fre-
quencies
1
Time from 0.9 V
DD
to valid
frequencies at all clock outputs
Time from OE rising edge to active
at outputs SSCLK1/2 (asynchro-
nous), F
OUT
= 133 MHz
Time from OE falling edge to active
at outputs SSCLK1/2 (asynchro-
nous), F
OUT
= 133 MHz
Min
—
—
—
—
—
—
—
Typ
1
12
30
85
145
1.2
15
Max
2
20
95
2
150
290
2
5
—
Unit
ns
ps rms
ps rms
ps
ps
ms
ns
Output Disable Time
t
OD
—
15
—
ns
Spread Spectrum Modulation Rate
3
SS
DEV
—
37
—
kHz
Note:
1. Example frequency configurations:
• 8 MHz, 100 MHz, 75 MHz
• 48 MHz, 100 MHz, 66 2/3 MHz
• 96 MHz, 133 1/3 MHz, 133 1/3 MHz
2. Jitter performance depends on configuration and programming parameters.
3. The SS modulation rate is a fixed ratio of the reference frequency with values in the range of 30 kHz to 50 kHz based on the
frequency plan.
Table 3.3. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
ESD Protection (Human Body Mod-
el)
ESD Protection (Charge Device
Model)
ESD Protection (Machine Model)
Note:
1. While using multiple power supplies, the Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power
supply sequencing is not required.
Symbol
V
DD
V
IN
T
S
T
A
ESD
HBM
ESD
CDM
ESD
MM
Relative to V
SS
Non-functional
Functional, I-Grade
JEDEC (JESD 22-A114)
JEDEC (JESD 22-C101)
JEDEC (JESD 22-A115)
Condition
Min
–0.5
–0.5
–65
–40
–4000
–1500
–200
Typ
—
—
—
—
—
—
—
Max
4.2
V
DD
+0.5
150
85
4000
1500
200
Unit
V
V
°C
°C
V
V
V
silabs.com
| Smart. Connected. Energy-friendly.
Rev. 1.0 | 4
京公网安备 11010802033920号
EEWORLD
