2Gb, 3V Multiple I/O Serial Flash Memory
Features
Micron Serial NOR Flash Memory
3V, Multiple I/O, 4KB, 32KB, 64KB Sector Erase
MT25QL02GC
Features
• SPI-compatible serial bus interface
• Single and double transfer rate (STR/DTR)
• Clock frequency
– 133 MHz (MAX) for all protocols in STR
– 66 MHz (MAX) for all protocols in DTR
• Dual/quad I/O commands for increased through-
put up to 65 MB/s
• Supported protocols in both STR and DTR
– Extended I/O protocol
– Dual I/O protocol
– Quad I/O protocol
• Execute-in-place (XIP)
• PROGRAM/ERASE SUSPEND operations
• Volatile and nonvolatile configuration settings
• Software reset
• Additional reset pin for selected part numbers
• 3-byte and 4-byte address modes – enable memory
access beyond 128Mb
• Dedicated 64-byte OTP area outside main memory
– Readable and user-lockable
– Permanent lock with PROGRAM OTP command
• Erase capability
– Sector erase 64KB uniform granularity
– Subsector erase 4KB, 32KB granularity
• Security and write protection
– Volatile and nonvolatile locking and software
write protection for each 64KB sector
– Nonvolatile configuration locking
– Password protection
– Hardware write protection: nonvolatile bits
(BP[3:0] and TB) define protected area size
– Program/erase protection during power-up
– CRC detects accidental changes to raw data
• Electronic signature
– JEDEC-standard 3-byte signature (BA20h)
– Extended device ID: two additional bytes identify
device factory options
• JESD47H-compliant
– Minimum 100,000 ERASE cycles per sector
– Data retention: 20 years (TYP)
Options
• Voltage
– 2.7–3.6V
• Density
– 1Gb
• Device stacking
– Monolithic
• Lithography
– 45nm
• Die revision
• Pin configuration
– RESET and HOLD#
• Production status
– Engineering samples
• Operating temperature range
– From –40°C to +85°C
– From –40°C to +105°C
• Special options
– Standard
– Automotive
• Standard security
• Packages – JEDEC-standard, RoHS-
compliant
– 24-ball T-PBGA 05/6mm x 8mm
(TBGA24)
• Sector Size
– 64KB
Marking
L
01G
A
B
A
8
ES
IT
AT
S
A
0
12
E
PDF: 09005aef8579b8b8
qlks_2gb_3V_45nm.pdf - Rev. B 07/14 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
2Gb, 3V Multiple I/O Serial Flash Memory
Features
Part Number Ordering
Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers
by using Micron’s part catalog search at
www.micron.com.
To compare features and specifications by device type,
visit
www.micron.com/products.
Contact the factory for devices not found.
Figure 1: Part Number Ordering Information
MT 25Q L
Micron Technology
Part Family
25Q = SPI NOR
Voltage
L = 2.7–3.6V
U = 1.7–2.0V
Density
064 = 64Mb (8MB)
128 = 128Mb (16MB)
256 = 256Mb (32MB)
512 = 512Mb (64MB)
01G = 1Gb (128MB)
02G = 2Gb (256MB)
Stack
A = 1 die/1 S#
B = 2 die/1 S#
C = 4 die/1 S#
Litho
B = 45nm
Die Revision
A = Rev. A
Pin Configuration Option
1 = HOLD# pin
3 = RESET# pin
8 = RESET# & HOLD# pin
Sector size
E = 64KB
xxx
A
BA
1
E
SF - 0
S
IT
ES
Production Status
Blank = Production
ES = Engineering samples
QS = Qualification samples
Operating Temperature
IT = –40°C to +85°C
AT = –40°C to +105°C (Grade 2 AEC-Q100)
Special Options
S = Standard
A = Automotive quality
Security Features
0 = Standard default security
Package Codes
12 = 24-ball T-PBGA, 05/6 x 8mm (5 x 5 array)
14 = 24-ball T-PBGA, 05/6 x 8mm (4 x 6 array)
SC = 8-pin SOP2, 150 mil
SE = 8-pin SOP2, 208 mil
SF = 16-pin SOP2, 300 mil
W7 = 8-pin W-PDFN, 6 x 5 mm
W9 = 8-pin W-PDFN, 8 x 6mm
PDF: 09005aef8579b8b8
qlks_2gb_3V_45nm.pdf - Rev. B 07/14 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
2Gb, 3V Multiple I/O Serial Flash Memory
Features
Contents
Device Description ........................................................................................................................................... 8
Device Diagram ............................................................................................................................................ 9
Advanced Security Protection ....................................................................................................................... 9
Signal Assignments ......................................................................................................................................... 10
Signal Descriptions ......................................................................................................................................... 11
Package Dimensions – 24-Ball T-PBGA ............................................................................................................ 12
Memory Organization .................................................................................................................................... 13
Memory Map – 2Gb Density ............................................................................................................................ 14
Status Register ................................................................................................................................................ 15
Block Protection Settings ............................................................................................................................ 16
Flag Status Register ......................................................................................................................................... 17
Extended Address Register .............................................................................................................................. 18
Internal Configuration Register ....................................................................................................................... 19
Nonvolatile Configuration Register .................................................................................................................. 20
Volatile Configuration Register ........................................................................................................................ 22
Supported Clock Frequencies ..................................................................................................................... 23
Enhanced Volatile Configuration Register ........................................................................................................ 24
Security Registers ........................................................................................................................................... 25
Sector Protection Security Register .................................................................................................................. 26
Nonvolatile and Volatile Sector Lock Bits Security ............................................................................................ 27
Volatile Lock Bit Security Register .................................................................................................................... 27
Device ID Data ............................................................................................................................................... 28
Serial Flash Discovery Parameter Data ............................................................................................................. 29
Command Definitions .................................................................................................................................... 34
Operations in Stacked Devices .................................................................................................................... 39
Software RESET Operations ............................................................................................................................ 40
RESET ENABLE and RESET MEMORY Commands ....................................................................................... 40
READ ID Operations ....................................................................................................................................... 41
READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 41
READ SERIAL FLASH DISCOVERY PARAMETER Operation .............................................................................. 42
READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 42
READ MEMORY Operations ............................................................................................................................ 43
4-BYTE READ MEMORY Operations ................................................................................................................ 43
READ MEMORY Operations Timings ............................................................................................................... 44
WRITE ENABLE/DISABLE Operations ............................................................................................................. 54
READ REGISTER Operations ........................................................................................................................... 56
WRITE REGISTER Operations ......................................................................................................................... 57
CLEAR FLAG STATUS REGISTER Operation ..................................................................................................... 59
PROGRAM Operations .................................................................................................................................... 60
4-BYTE PROGRAM Operations ........................................................................................................................ 61
PROGRAM Operations Timings ....................................................................................................................... 62
ERASE Operations .......................................................................................................................................... 66
SUSPEND/RESUME Operations ..................................................................................................................... 68
PROGRAM/ERASE SUSPEND Operations .................................................................................................... 68
PROGRAM/ERASE RESUME Operations ...................................................................................................... 68
ONE-TIME PROGRAMMABLE Operations ....................................................................................................... 70
READ OTP ARRAY Command ...................................................................................................................... 70
PROGRAM OTP ARRAY Command .............................................................................................................. 70
ADDRESS MODE Operations .......................................................................................................................... 72
QUAD PROTOCOL Operations ........................................................................................................................ 72
PDF: 09005aef8579b8b8
qlks_2gb_3V_45nm.pdf - Rev. B 07/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
2Gb, 3V Multiple I/O Serial Flash Memory
Features
ENTER or RESET QUAD INPUT/OUTPUT MODE Command .......................................................................
CYCLIC REDUNDANCY CHECK Operations ....................................................................................................
State Table .....................................................................................................................................................
XIP Mode .......................................................................................................................................................
Activate or Terminate XIP Using Volatile Configuration Register ...................................................................
Activate or Terminate XIP Using Nonvolatile Configuration Register .............................................................
Confirmation Bit Settings Required to Activate or Terminate XIP ..................................................................
Terminating XIP After a Controller and Memory Reset .................................................................................
Power-Up and Power-Down ............................................................................................................................
Power-Up and Power-Down Requirements ..................................................................................................
Power Loss and Interface Rescue .....................................................................................................................
Recovery ....................................................................................................................................................
Power Loss Recovery ...................................................................................................................................
Interface Rescue .........................................................................................................................................
Absolute Ratings and Operating Conditions .....................................................................................................
DC Characteristics and Operating Conditions ..................................................................................................
AC Characteristics and Operating Conditions ..................................................................................................
AC Reset Specifications ...................................................................................................................................
Program/Erase Specifications .........................................................................................................................
Revision History .............................................................................................................................................
Rev. B - 07/14Rev. A – 12/13 .........................................................................................................................
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PDF: 09005aef8579b8b8
qlks_2gb_3V_45nm.pdf - Rev. B 07/14 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
2Gb, 3V Multiple I/O Serial Flash Memory
Features
List of Figures
Figure 1: Part Number Ordering Information .................................................................................................... 2
Figure 2: Block Diagram .................................................................................................................................. 8
Figure 3: Logic Diagram ................................................................................................................................... 9
Figure 4: 24-Ball TBGA (Balls Down) .............................................................................................................. 10
Figure 5: 5 x 5 ball grid array – 6mm x 8mm (Package Code: 12) ....................................................................... 12
Figure 6: Block Diagram ................................................................................................................................ 13
Figure 7: Internal Configuration Register ........................................................................................................ 19
Figure 8: Sector and Password Protection ....................................................................................................... 25
Figure 9: RESET ENABLE and RESET MEMORY Command ............................................................................. 40
Figure 10: READ ID and MULTIPLE I/O READ ID Commands ......................................................................... 41
Figure 11: READ SERIAL FLASH DISCOVERY PARAMETER Command – 5Ah ................................................... 42
Figure 12: READ – 03h/13h
3
........................................................................................................................... 44
Figure 13: FAST READ – 0Bh/0Ch
3
................................................................................................................. 45
Figure 14: DUAL OUTPUT FAST READ – 3Bh/3Ch
3
......................................................................................... 46
Figure 15: DUAL INPUT/OUTPUT FAST READ – BBh/BCh
3
............................................................................ 46
Figure 16: QUAD OUTPUT FAST READ – 6Bh/6Ch
3
........................................................................................ 47
Figure 17: QUAD INPUT/OUTPUT FAST READ – EBh/ECh
3
............................................................................ 48
Figure 18: QUAD INPUT/OUTPUT WORD READ – E7h
3
................................................................................. 49
Figure 19: DTR FAST READ – 0Dh/E0h
3
.......................................................................................................... 50
Figure 20: DTR DUAL OUTPUT FAST READ – 3Dh
3
........................................................................................ 51
Figure 21: DTR DUAL INPUT/OUTPUT FAST READ – BDh
3
............................................................................ 51
Figure 22: DTR QUAD OUTPUT FAST READ – 6Dh
3
........................................................................................ 52
Figure 23: DTR QUAD INPUT/OUTPUT FAST READ – EDh
3
............................................................................ 53
Figure 24: WRITE ENABLE and WRITE DISABLE Timing ................................................................................. 55
Figure 25: READ REGISTER Timing ................................................................................................................ 56
Figure 26: WRITE REGISTER Timing .............................................................................................................. 58
Figure 27: CLEAR FLAG STATUS REGISTER Timing ........................................................................................ 59
Figure 28: PAGE PROGRAM Command .......................................................................................................... 62
Figure 29: DUAL INPUT FAST PROGRAM Command ...................................................................................... 63
Figure 30: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 63
Figure 31: QUAD INPUT FAST PROGRAM Command ..................................................................................... 64
Figure 32: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 65
Figure 33: SUBSECTOR and SECTOR ERASE Timing ....................................................................................... 67
Figure 34: BULK ERASE Timing ...................................................................................................................... 67
Figure 35: PROGRAM/ERASE SUSPEND or RESUME Timing .......................................................................... 69
Figure 36: READ OTP Command .................................................................................................................... 70
Figure 37: PROGRAM OTP Command ............................................................................................................ 71
Figure 38: XIP Mode Directly After Power-On .................................................................................................. 76
Figure 39: Power-Up Timing .......................................................................................................................... 79
Figure 40: AC Timing Input/Output Reference Levels ...................................................................................... 82
Figure 41: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 87
Figure 42: Reset Enable and Reset Memory Timing ......................................................................................... 87
Figure 43: Serial Input Timing ........................................................................................................................ 87
Figure 44: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 88
Figure 45: Hold Timing .................................................................................................................................. 88
Figure 46: Output Timing .............................................................................................................................. 88
PDF: 09005aef8579b8b8
qlks_2gb_3V_45nm.pdf - Rev. B 07/14 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2012 Micron Technology, Inc. All rights reserved.
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