64Mb: x8, x16 SDRAM
Features
SDR SDRAM
MT48LC8M8A2 – 2 Meg x 8 x 4 Banks
MT48LC4M16A2 – 1 Meg x 16 x 4 Banks
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode (not available on AAT devices)
• Refresh
– 64ms, 4096-cycle refresh (15.6µs/row)
(industrial)
– 16ms, 4096-cycle refresh (3.9µs/row)
(automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• AEC-Q100
• PPAP submission
• 8D response time
Options
• Configuration
– 8 Meg x 8 (2 Meg x 8 x 4 banks)
– 4 Meg x 16 (1 Meg x 16 x 4 banks)
• Write recovery (
t
WR)
–
t
WR = 2 CLK
1
• Plastic package – OCPL
2
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free,
RoHS-compliant
– 54-ball VFBGA 8mm x 8mm
(x16 only)
– 54-ball VFBGA 8mm x 16mm, Pb-
free, RoHS-compliant (x16 only)
• Timing – cycle time
– 6ns @ CL = 3 (x16 only)
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
• Self refresh
– Standard
– Low power
• Operating temperature range
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
• Revision
Notes:
Marking
8M8
4M16
A2
TG
P
F4
B4
3
-6A
-75
-7E
None
L
AIT
AAT
3
:J
1. See Micron technical note TN-48-05 on
Micron's Web site.
2. Off-center parting line.
3. Contact Micron for availability.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-6A
-7E
-75
-7E
-75
Clock
Frequency
167 MHz
143 MHz
133 MHz
133 MHz
100 MHz
Access Time
CL = 2
–
–
–
5.4ns
6ns
CL = 3
5.5ns
5.4ns
5.4ns
–
–
Setup Time
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
Hold Time
1ns
0.8ns
0.8ns
0.8ns
0.8ns
09005aef84942e37
64mb_ait_aat_sdr.pdf - Rev. D 6/18 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
64Mb: x8, x16 SDRAM
Features
Table 2: Address Table
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column
addressing
8 Meg x 8
2 Meg x 8 x 4 banks
4K
4K A[11:0]
4 BA[1:0]
512 A[8:0]
4 Meg x 16
1 Meg x 16 x 4 banks
4K
4K A[11:0]
4 BA[1:0]
256 A[7:0]
Table 3: 64Mb SDR Part Numbering
Part Numbers
MT48LC8M8A2TG
MT48LC8M8A2P
MT48LC4M16A2TG
MT48LC4M16A2P
MT48LC4M16A2B4
1
MT48LC4M16A2F4
1
Note:
Architecture
8 Meg x 8
8 Meg x 8
4 Meg x 16
4 Meg x 16
4 Meg x 16
4 Meg x 16
Package
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-ball VFBGA
54-ball VFBGA
1. FBGA Device Decoder: www.micron.com/decoder.
09005aef84942e37
64mb_ait_aat_sdr.pdf - Rev. D 6/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
64Mb: x8, x16 SDRAM
Features
Contents
Important Notes and Warnings ......................................................................................................................... 7
General Description ......................................................................................................................................... 7
Automotive Temperature .............................................................................................................................. 8
Functional Block Diagrams ............................................................................................................................... 9
Pin and Ball Assignments and Descriptions ..................................................................................................... 11
Package Dimensions ....................................................................................................................................... 14
Temperature and Thermal Impedance ............................................................................................................ 16
Electrical Specifications .................................................................................................................................. 19
Electrical Specifications – I
DD
Parameters ........................................................................................................ 21
Electrical Specifications – AC Operating Conditions ......................................................................................... 23
Functional Description ................................................................................................................................... 27
Commands .................................................................................................................................................... 28
COMMAND INHIBIT .................................................................................................................................. 28
NO OPERATION (NOP) ............................................................................................................................... 29
LOAD MODE REGISTER (LMR) ................................................................................................................... 29
ACTIVE ...................................................................................................................................................... 29
READ ......................................................................................................................................................... 30
WRITE ....................................................................................................................................................... 31
PRECHARGE .............................................................................................................................................. 32
BURST TERMINATE ................................................................................................................................... 32
Truth Tables ................................................................................................................................................... 33
Initialization .................................................................................................................................................. 38
Mode Register ................................................................................................................................................ 40
Burst Length .............................................................................................................................................. 42
Burst Type .................................................................................................................................................. 42
CAS Latency ............................................................................................................................................... 44
Operating Mode ......................................................................................................................................... 44
Write Burst Mode ....................................................................................................................................... 44
Bank/Row Activation ...................................................................................................................................... 45
READ Operation ............................................................................................................................................. 46
WRITE Operation ........................................................................................................................................... 55
Burst Read/Single Write .............................................................................................................................. 62
PRECHARGE Operation .................................................................................................................................. 63
Auto Precharge ........................................................................................................................................... 63
AUTO REFRESH Operation ............................................................................................................................. 75
SELF REFRESH Operation ............................................................................................................................... 77
Power-Down .................................................................................................................................................. 79
Clock Suspend ............................................................................................................................................... 80
Revision History ............................................................................................................................................. 83
Rev. D – 6/18 .............................................................................................................................................. 83
Rev. C – 11/13 ............................................................................................................................................. 83
Rev. B – 3/12 ............................................................................................................................................... 83
Rev. A – 12/11 ............................................................................................................................................. 83
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64mb_ait_aat_sdr.pdf - Rev. D 6/18 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
64Mb: x8, x16 SDRAM
Features
List of Figures
Figure 1: 8 Meg x 8 Functional Block Diagram ................................................................................................... 9
Figure 2: 4 Meg x 16 Functional Block Diagram ............................................................................................... 10
Figure 3: 54-Pin TSOP (Top View) .................................................................................................................. 11
Figure 4: 54-Ball VFBGA x16 (Top View) ......................................................................................................... 12
Figure 5: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P ......................................................................... 14
Figure 6: 54-Ball VFBGA (8mm x 8mm) – Package Codes F4/B4 ....................................................................... 15
Figure 7: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 17
Figure 8: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) .............................................. 18
Figure 9: ACTIVE Command .......................................................................................................................... 29
Figure 10: READ Command ........................................................................................................................... 30
Figure 11: WRITE Command ......................................................................................................................... 31
Figure 12: PRECHARGE Command ................................................................................................................ 32
Figure 13: Initialize and Load Mode Register .................................................................................................. 39
Figure 14: Mode Register Definition ............................................................................................................... 41
Figure 15: CAS Latency .................................................................................................................................. 44
Figure 16: Example: Meeting
t
RCD (MIN) When 2 <
t
RCD (MIN)/
t
CK < 3 .......................................................... 45
Figure 17: Consecutive READ Bursts .............................................................................................................. 47
Figure 18: Random READ Accesses ................................................................................................................ 48
Figure 19: READ-to-WRITE ............................................................................................................................ 49
Figure 20: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 50
Figure 21: READ-to-PRECHARGE .................................................................................................................. 50
Figure 22: Terminating a READ Burst ............................................................................................................. 51
Figure 23: Alternating Bank Read Accesses ..................................................................................................... 52
Figure 24: READ Continuous Page Burst ......................................................................................................... 53
Figure 25: READ – DQM Operation ................................................................................................................ 54
Figure 26: WRITE Burst ................................................................................................................................. 55
Figure 27: WRITE-to-WRITE .......................................................................................................................... 56
Figure 28: Random WRITE Cycles .................................................................................................................. 57
Figure 29: WRITE-to-READ ............................................................................................................................ 57
Figure 30: WRITE-to-PRECHARGE ................................................................................................................. 58
Figure 31: Terminating a WRITE Burst ............................................................................................................ 59
Figure 32: Alternating Bank Write Accesses ..................................................................................................... 60
Figure 33: WRITE – Continuous Page Burst ..................................................................................................... 61
Figure 34: WRITE – DQM Operation ............................................................................................................... 62
Figure 35: READ With Auto Precharge Interrupted by a READ ......................................................................... 64
Figure 36: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 65
Figure 37: READ With Auto Precharge ............................................................................................................ 66
Figure 38: READ Without Auto Precharge ....................................................................................................... 67
Figure 39: Single READ With Auto Precharge .................................................................................................. 68
Figure 40: Single READ Without Auto Precharge ............................................................................................. 69
Figure 41: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 70
Figure 42: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 70
Figure 43: WRITE With Auto Precharge ........................................................................................................... 71
Figure 44: WRITE Without Auto Precharge ..................................................................................................... 72
Figure 45: Single WRITE With Auto Precharge ................................................................................................. 73
Figure 46: Single WRITE Without Auto Precharge ............................................................................................ 74
Figure 47: Auto Refresh Mode ........................................................................................................................ 76
Figure 48: Self Refresh Mode .......................................................................................................................... 78
Figure 49: Power-Down Mode ........................................................................................................................ 79
Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 80
09005aef84942e37
64mb_ait_aat_sdr.pdf - Rev. D 6/18 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
64Mb: x8, x16 SDRAM
Features
Figure 51: Clock Suspend During READ Burst ................................................................................................. 81
Figure 52: Clock Suspend Mode ..................................................................................................................... 82
09005aef84942e37
64mb_ait_aat_sdr.pdf - Rev. D 6/18 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
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