GS8161E18D(GT/D)/GS8161E32D(D)/GS8161E36D(GT/D)
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
1M x 18, 512K x 32, 512K x 36
18Mb SyncBurst SRAMs
400 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump BGA package
• RoHS-compliant 100-pin TQFP and 165-bump BGA available
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The
GS8161E18D(GT/D)/GS8161E32D(D)/GS8161D36D(GT/D)
is
a DCD (Dual Cycle Deselect) pipelined synchronous SRAM.
SCD (Single Cycle Deselect) versions are also available. DCD
SRAMs pipeline disable commands to the same degree as read
commands. DCD RAMs hold the deselect command for one
full cycle and then begin turning off their outputs just after the
second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The
GS8161E18D(GT/D)/GS8161E32D(D)/GS8161D36D(GT/D)
operates on a 3.3 V or 2.5 V power supply. All input are 3.3 V
and 2.5 V compatible. Separate output power (V
DDQ
) pins are
used to decouple output noise from the internal circuits and are
3.3 V and 2.5 V compatible.
Functional Description
Applications
The
GS8161E18D(GT/D)/GS8161E32D(D)/GS8161D36D(GT/D)
is
an 18,874,368-bit high performance synchronous SRAM with
a 2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Parameter Synopsis
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
-400
2.5
2.5
370
430
4.0
4.0
275
315
1/37
-375
2.5
2.66
350
410
4.2
4.2
265
300
-333
2.5
3.3
310
365
4.5
4.5
255
285
-250
2.5
4.0
250
290
5.5
5.5
220
250
-200
3.0
5.0
210
240
6.5
6.5
205
225
-150
3.8
6.7
185
200
7.5
7.5
190
205
Unit
ns
ns
mA
mA
ns
ns
mA
mA
© 2011, GSI Technology
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.03b 9/2013
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161E18D(GT/D)/GS8161E32D(D)/GS8161E36D(GT/D)
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
NC
BW
B
A
, B
B,
B
C
, B
D
CK
GW
E
1
G
ADV
ADSP, ADSC
ZZ
TMS
TDI
TDO
TCK
FT
LBO
V
DD
V
SS
V
DDQ
Type
I
I
I/O
—
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.03b 9/2013
4/37
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Analog electronics
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