EEWORLDEEWORLDEEWORLD

Part Number

Search

GS8673ED18BGK-675S

Description
Static random access memory 1.2/1.5V 4M x 18 72M
Categorysemiconductor    Memory IC    Static random access memory   
File Size179KB,25 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Environmental Compliance
Download Datasheet Parametric Compare View All

GS8673ED18BGK-675S Online Shopping

Suppliers Part Number Price MOQ In stock  
GS8673ED18BGK-675S - - View Buy Now

GS8673ED18BGK-675S Overview

Static random access memory 1.2/1.5V 4M x 18 72M

GS8673ED18BGK-675S Parametric

Parameter NameAttribute value
MakerGSI Technology
Product Categorystatic random access memory
storage72 Mbit
organize4 M x 18
maximum clock frequency675 MHz
Interface TypeParallel
Supply voltage - max.1.4 V
Supply voltage - min.1.3 V
Minimum operating temperature0 C
Maximum operating temperature+ 85 C
Installation styleSMD/SMT
Package/boxBGA-260
EncapsulationTray
storage typeQDR-III
seriesGS8673ED18BGK
typeSigmaQuad-IIIe B4
Factory packaging quantity8
GS8673ED18/36BK-725S/625S/550S
260 Pin BGA
Commercial Temp
Industrial Temp
Features
• For use with GSI SRAM Port IP
• 2Mb x 36 and 4Mb x 18 organizations available
• 725 MHz maximum operating frequency
• 725 MT/s peak transaction rate (in millions per second)
• 104 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• Burst of 4 Read and Write operations
• 3 cycle Read Latency
• On-chip ECC with virtually zero SER
• 1.35V core voltage
• 1.2V or 1.35V or 1.5V I/O interface (HSTL or SSTL)
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260 pin, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
–GK: 6/6 RoHS-compliant package
72Mb SigmaQuad-IIIe™
Burst of 4 ECCRAM™
Up to 725 MHz
1.35V V
DD
1.2V or 1.35V or 1.5V V
DDQ
Clocking and Addressing Schemes
The GS8673ED18/36BK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IIIe B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B4 ECCRAM is always two address
pins less than the advertised index depth (e.g. the 4M x 18 has
1M addressable index).
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
On-Chip ECC
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Parameter Synopsis
Speed Grade
-725S
-625S
-550S
Max Operating Frequency
725 MHz
625 MHz
550 MHz
Read Latency
3 cycles
3 cycles
3 cycles
V
DD
1.3V to 1.4V
1.3V to 1.4V
1.3V to 1.4V
Rev: 1.04 6/2015
1/25
© 2012, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ED18BGK-675S Related Products

GS8673ED18BGK-675S GS8673ED36BK-675S GS8673ED36BGK-675S GS8673ED36BGK-675IS GS8673ED18BK-675S GS8673ED36BK-675IS GS8673ED18BGK-675IS
Description Static random access memory 1.2/1.5V 4M x 18 72M SRAM 1.2/1.5V 2M x 36 72M SRAM 1.2/1.5V 2M x 36 72M SRAM 1.2/1.5V 2M x 36 72M SRAM 1.2/1.5V 4M x 18 72M SRAM 1.2/1.5V 2M x 36 72M SRAM 1.2/1.5V 4M x 18 72M
Product Category static random access memory SRAM SRAM SRAM SRAM SRAM SRAM
Interface Type Parallel Parallel Parallel Parallel Parallel Parallel Parallel
Product Attribute - Attribute Value Attribute Value Attribute Value Attribute Value Attribute Value Attribute Value
Manufacturer - GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology
Memory Size - 72 Mbit 72 Mbit 72 Mbit 72 Mbit 72 Mbit 72 Mbit
Organization - 2 M x 36 2 M x 36 2 M x 36 4 M x 18 2 M x 36 4 M x 18
Maximum Clock Frequency - 675 MHz 675 MHz 675 MHz 675 MHz 675 MHz 675 MHz
Supply Voltage - Max - 1.4 V 1.4 V 1.4 V 1.4 V 1.4 V 1.4 V
Supply Voltage - Min - 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V
Minimum Operating Temperature - 0 C 0 C - 40 C 0 C - 40 C - 40 C
Maximum Operating Temperature - + 85 C + 85 C + 100 C + 85 C + 100 C + 100 C
Mounting Style - SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT
Package / Case - BGA-260 BGA-260 BGA-260 BGA-260 BGA-260 BGA-260
Packaging - Tray Tray Tray Tray Tray Tray
Memory Type - QDR-III QDR-III QDR-III QDR-III QDR-III QDR-III
Type - SigmaQuad-IIIe B4 SigmaQuad-IIIe B4 SigmaQuad-IIIe B4 SigmaQuad-IIIe B4 SigmaQuad-IIIe B4 SigmaQuad-IIIe B4
Moisture Sensitive - Yes Yes Yes Yes Yes Yes
Factory Pack Quantity - 8 8 8 8 8 8
I am preparing for the national competition and want to draw a board to practice. Do you have any good projects to recommend?
I really don’t want to draw development boards anymore. Do you have any good projects to recommend? . . . ....
WZH70246 PCB Design
About stepper motor control
Dear experts: This is a two-phase motor, how do I connect it?I don't know if the wiring I connected is wrong or if there is a problem with the program. It works fine when the software is simulated, bu...
czc568 MCU
Where can I download detailed documents on wireless protocols?
I just started learning GPRS development and wanted to look at some wireless communication protocols. I googled but couldn't find any, so I would like to ask where I can download complete documents of...
xiaomi_1981 Embedded System
Help on the design of reaction speed tester (MCS-51 single chip microcomputer)
I hope the experts can help me . Thanks in advance! The requirements are as follows: 1. Be able to complete the test of a person's reaction speed and display the results on the LED digital display. 2....
xupc 51mcu
Direct torque dsp control of asynchronous ac motor
How to design direct torque system of AC asynchronous motor using TMS series DSP chip?...
wawals DSP and ARM Processors
inductance
Inductance In the circuit, inductance is often represented by "L" plus a number, such as: L6 represents an inductor numbered 6. The inductor coil is made by winding an insulated wire around an insulat...
dianzijie5 MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2744  2879  2191  2812  1747  56  58  45  57  36 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号