GS8673ED18/36BK-675/625/550/500
260-Ball BGA
Commercial Temp
Industrial Temp
Features
• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write SigmaQuad-IIIe™ Interface
• Separate I/O Bus
• Double Data Rate interface
• Burst of 4 Read and Write
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35V nominal V
DD
• 1.2V JESD8-16A BIC-3 Compliant Interface
• 1.5V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT pin for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
–GK: 6/6 RoHS-compliant package
72Mb SigmaQuad-IIIe™
Burst of 4 ECCRAM™
Clocking and Addressing Schemes
675 MHz–500 MHz
1.35V V
DD
1.2V to 1.5V V
DDQ
The GS8673ED18/36BK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ dual, single-ended master
clocks, CK and CK. These clocks are single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. CK and CK are used to control the address and control
input registers, as well as all output timing.
The KD and KD clocks are dual mesochronous (with respect to
CK and CK) input clocks that are used to control the data input
registers. Consequently, data input setup and hold windows
can be optimized independently of address and control input
setup and hold windows.
Each internal read and write operation in a SigmaQuad-IIIe B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B4 ECCRAM is always two address
pins less than the advertised index depth (e.g. the 4M x 18 has
1M addressable index).
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles, etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
Parameter Synopsis
Speed Bin
-675
-625
-550
-500
Operating Frequency
675 / 450 MHz
625 / 400 MHz
550 / 375 MHz
500 / 333 MHz
Data Rate (per pin)
1350 / 900 Mbps
1250 / 800 Mbps
1100 / 750 Mbps
1000 / 666 Mbps
Read Latency
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
V
DD
1.3V to 1.4V
1.3V to 1.4V
1.25V to 1.4V
1.25V to 1.4V
Note: Please contact GSI for availability of 714 MHz devices.
Rev: 1.07 12/2017
1/31
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8673ED18/36BK-675/625/550/500
4M x 18 (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
Q17
V
SS
Q16
V
SS
Q15
Q14
V
SS
CQ1
CQ1
V
SS
NU
O
NU
O
V
SS
NU
O
V
SS
NU
O
V
SS
V
DD
2
V
DDQ
NU
O
V
DDQ
NU
O
V
DDQ
NU
O
NU
O
V
DDQ
NU
O
V
DDQ
V
SS
Q13
V
DDQ
Q12
Q11
V
DDQ
Q10
V
DDQ
Q9
V
DDQ
3
V
DD
V
SS
D17
V
SS
D16
V
SS
D15
D14
V
SS
V
REF
QVLD1
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
4
V
DDQ
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
ss
D13
V
DDQ
D12
D11
V
DD
D10
V
DDQ
D9
V
DDQ
5
MCL
MVQ
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD1
KD1
V
SS
DLL
V
SS
MCH
V
SS
NU
I
V
SS
TCK
TDO
6
MCH
(CFG)
MCH
(B4M)
7
MCL
NC
(RSVD)
8
ZQ
MCH
(SIOM)
9
PZT1
PZT0
V
SS
NC
(144 Mb)
10
V
DDQ
D0
V
DDQ
D1
V
DD
D2
D3
V
DDQ
D4
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
V
DDQ
11
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD0
V
SS
D5
D6
V
SS
D7
V
SS
D8
V
SS
V
DD
12
V
DDQ
Q0
V
DDQ
Q1
V
DDQ
Q2
Q3
V
DDQ
Q4
V
DDQ
V
SS
NU
O
V
DDQ
NU
O
NU
O
V
DDQ
NU
O
V
DDQ
NU
O
V
DDQ
13
V
DD
V
SS
NU
O
V
SS
NU
O
V
SS
NU
O
NU
O
V
SS
CQ0
CQ0
V
SS
Q5
Q6
V
SS
Q7
V
SS
Q8
V
SS
V
DD
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
(x18)
V
DD
NC
(288 Mb)
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
NU
I
(B2)
V
SS
V
DDQ
MZT1
W
V
SS
CK
CK
V
SS
R
MZT0
V
DDQ
V
SS
ADZT1
V
DD
NC
(RSVD)
V
SS
SA
V
SS
SA
V
SS
KD0
KD0
V
SS
MCH
V
SS
RST
V
SS
NU
I
V
SS
TMS
TDI
RLM0
ZT
MCL
MCL
RLM1
Notes:
1. Pins 5A and 7A are reserved for future use. They must be tied Low in this device.
2. Pins 5R and 9N are reserved for future use. They must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.
8. Pin 9D is reserved as address pin SA for 144 Mb devices. It is a true no connect in this device.
9. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
10. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
11. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.
12. Pins 7B and 7W are reserved for future use. They are true no connects in this device.
Rev: 1.07 12/2017
2/31
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8673ED18/36BK-675/625/550/500
2M x 36 (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
Q26
V
SS
Q25
V
SS
Q24
Q23
V
SS
CQ1
CQ1
V
SS
Q30
Q29
V
SS
Q28
V
SS
Q27
V
SS
V
DD
2
V
DDQ
Q35
V
DDQ
Q34
V
DDQ
Q33
Q32
V
DDQ
Q31
V
DDQ
V
SS
Q22
V
DDQ
Q21
Q20
V
DDQ
Q19
V
DDQ
Q18
V
DDQ
3
V
DD
V
SS
D26
V
SS
D25
V
SS
D24
D23
V
SS
V
REF
QVLD1
4
V
DDQ
D35
V
DDQ
D34
V
DD
D33
D32
V
DDQ
D31
V
DD
V
SS
D22
V
DDQ
D21
D20
V
DD
D19
V
DDQ
D18
V
DDQ
5
MCL
MVQ
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD1
KD1
V
SS
DLL
V
SS
MCH
V
SS
NU
I
V
SS
TCK
TDO
6
MCL
(CFG)
MCH
(B4M)
7
MCL
NC
(RSVD)
8
ZQ
MCH
(SIOM)
9
PZT1
PZT0
V
SS
NC
(144 Mb)
10
V
DDQ
D0
V
DDQ
D1
V
DD
D2
D3
V
DDQ
D4
V
DD
V
SS
D13
V
DDQ
D14
D15
V
DD
D16
V
DDQ
D17
V
DDQ
11
V
DD
V
SS
D9
V
SS
D10
V
SS
D11
D12
V
SS
V
REF
QVLD0
V
SS
D5
D6
V
SS
D7
V
SS
D8
V
SS
V
DD
12
V
DDQ
Q0
V
DDQ
Q1
V
DDQ
Q2
Q3
V
DDQ
Q4
V
DDQ
V
SS
Q13
V
DDQ
Q14
Q15
V
DDQ
Q16
V
DDQ
Q17
V
DDQ
13
V
DD
V
SS
Q9
V
SS
Q10
V
SS
Q11
Q12
V
SS
CQ0
CQ0
V
SS
Q5
Q6
V
SS
Q7
V
SS
Q8
V
SS
V
DD
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
NU
I
(x18)
V
DD
NC
(288 Mb)
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
NU
I
(B2)
V
SS
V
DDQ
MZT1
W
V
SS
CK
CK
V
SS
R
MZT0
V
DDQ
V
SS
ADZT1
V
DD
NC
(RSVD)
V
SS
SA
V
SS
SA
V
SS
KD0
KD0
V
SS
MCH
V
SS
RST
V
SS
NU
I
V
SS
TMS
TDI
V
SS
D30
D29
V
SS
D28
V
SS
D27
V
SS
V
DD
RLM0
ZT
MCL
MCL
RLM1
Notes:
1. Pins 5A and 7A are reserved for future use. They must be tied Low in this device.
2. Pins 5R and 9N are reserved for future use. They must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.
8. Pin 9D is reserved as address pin SA for 144 Mb devices. It is a true no connect in this device.
9. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
10. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
11. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.
12. Pins 7B and 7W are reserved for future use. They are true no connects in this device.
Rev: 1.07 12/2017
3/31
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8673ED18/36BK-675/625/550/500
Pin Description
Symbol
SA
D[35:0]
Description
Address—Read
or Write Address is registered on
CK.
Write Data—Registered
on
KD
and
KD
during Write operations.
D[17:0]—x18 and x36.
D[35:18]—x36 only.
Read Data—Driven
by
CK
and
CK,
and synchronized with
CQ
and
CQ
during Read operations.
Q[17:0]—x18 and x36.
Q[35:18]—x36 only.
Read Data Valid—Driven
high one half cycle before valid Read Data.
Primary Input Clocks—Dual
single-ended. For Address and Control input latching, internal timing control,
and Read Data and Echo Clock output timing control.
Write Data Input Clocks—Dual
single-ended. For Write Data input latching.
KD0, KD0—latch Write Data (D[17:0] in x36, D[8:0] in x18).
KD1, KD1—latch Write Data (D[35:18] in x36, D[17:9] in x18).
Echo Clocks—Free
running source synchronous output clocks.
Read Enable—Registered
on
CK.
R = 0 initiates a Read operation.
Write Enable—Registered
on
CK.
W = 0 initiates a Write operation.
Address and Write Data Input Termination Pull-Up Enable—Registered
onCK.
ADZT1 = 0: enables termination pull-up on Address (SA), Write Data (D) inputs.
ADZT1 = 1: disables termination pull-up on Address (SA), Write Data (D) inputs.
DLL Enable—Weakly
pulled High internally.
DLL = 0: disables internal DLL.
DLL = 1: enables internal DLL.
Reset—Holds
the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Read Latency Select 1:0—Must
be tied High or Low.
RLM[1:0] = 00: reserved.
RLM[1:0] = 01: selects 2.0 cycle Read Latency.
RLM[1:0] = 10: selects 3.0 cycle Read Latency.
RLM[1:0] = 11: reserved.
Output Driver Impedance Control Resistor Input—Must
be connected to V
SS
through an external
resistor RQ to program output driver impedance.
Input Termination Impedance Control Resistor Input—Must
be connected to V
SS
through an external
resistor RT to program input termination impedance.
Type
Input
Input
Q[35:0]
QVLD[1:0]
CK, CK
KD[1:0],
KD[1:0]
CQ[1:0],
CQ[1:0]
R
W
ADZT1
Output
Output
Input
Input
Output
Input
Input
Input
DLL
Input
RST
Input
RLM[1:0]
Input
ZQ
ZT
Input
Input
Rev: 1.07 12/2017
4/31
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8673ED18/36BK-675/625/550/500
Pin Description (Continued)
Symbol
Description
Input Termination Mode Select—Selects
the termination mode used for all terminated inputs. Must be tied
High or Low.
MZT[1:0] = 00: disabled.
MZT[1:0] = 01: RT/2 Thevenin-equivalent (pull-up = RT, pull-down = RT).
MZT[1:0] = 10: RT Thevenin-equivalent (pull-up = 2*RT, pull-down = 2*RT).
MZT[1:0] = 11: reserved.
Input Termination Configuration Select—Selects
which inputs are terminated. Must be tied High or Low.
PZT[1:0] = 00: Write Data only.
PZT[1:0] = 01: Write Data, Input Clocks.
PZT[1:0] = 10: Write Data, Address, Control.
PZT[1:0] = 11: Write Data, Address, Control, Input Clocks.
I/O Voltage Select—Indicates
what voltage is supplied to the V
DDQ
pins. Must be tied High or Low.
MVQ = 0: Configure for 1.2V to 1.35V nominal V
DDQ
.
MVQ = 1: Configure for 1.5V nominal V
DDQ
.
Core Power Supply—1.35V
nominal core supply voltage.
I/O Power Supply—1.2V
to 1.5V nominal I/O supply voltage. Configurable via MVQ pin.
Input Reference Voltage—Input
buffer reference voltage.
Ground
JTAG Clock
JTAG Mode Select—Weakly
pulled High internally.
JTAG Data Input—Weakly
pulled High internally.
JTAG Data Output
Must Connect High—May
be tied to V
DDQ
directly or via a 1k resistor.
Must Connect Low—May
be tied to V
SS
directly or via a 1k resistor.
No Connect—There
is no internal chip connection to these pins. They may be left unconnected, or tied High
or Low.
Not Used, Input—There
is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied Low. They should not be tied
High.
Not Used, Output—There
is an internal chip connection to these output pins, but they are unused by the
device. Unused output pins are tri-stated internally. They should be left unconnected.
Type
MZT[1:0]
Input
PZT[1:0]
Input
MVQ
Input
V
DD
V
DDQ
V
REF
V
SS
TCK
TMS
TDI
TDO
MCH
MCL
NC
—
—
—
—
Input
Input
Input
Output
Input
Input
—
NU
I
NU
O
Input
Output
Rev: 1.07 12/2017
5/31
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
FPGA/CPLD
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