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GS81302T38GE-500

Description
Static random access memory 1.8 or 1.5V 4M x 36 144M
Categorysemiconductor    Memory IC    Static random access memory   
File Size2MB,30 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Environmental Compliance
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GS81302T38GE-500 Overview

Static random access memory 1.8 or 1.5V 4M x 36 144M

GS81302T38GE-500 Parametric

Parameter NameAttribute value
MakerGSI Technology
Product Categorystatic random access memory
storage144 Mbit
organize4 M x 36
maximum clock frequency500 MHz
Interface TypeParallel
Supply voltage - max.1.9 V
Supply voltage - min.1.7 V
Supply current—max.1.3 A
Minimum operating temperature0 C
Maximum operating temperature+ 70 C
Installation styleSMD/SMT
Package/boxBGA-165
EncapsulationTray
storage typeDDR-II
seriesGS81302T38GE
typeSigmaDDR-II+
Factory packaging quantity10
GS81302T06/11/20/38E-500/450/400/350
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaDDR
TM
Interface
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
144Mb SigmaDDR
TM
-II+
Burst of 2 SRAM
500 MHz–350 MHz
1.8 V V
DD
1.8 V or 1.5 V I/O
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS81302T06/11/20/38E SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
SigmaDDR-II™ Family Overview
The GS81302T06/11/20/38E are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302T06/11/20/38E SigmaDDR-II+
Parameter Synopsis
-500
tKHKH
tKHQV
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Rev: 1.03d 8/2017
1/29
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS81302T38GE-500 Related Products

GS81302T38GE-500 GS81302T38E-500 GS81302T11GE-350 GS81302T11GE-400 GS81302T11E-350 GS81302T06GE-450 GS81302T06E-450 GS81302T11E-400 GS81302T20E-400I GS81302T11GE-450
Description Static random access memory 1.8 or 1.5V 4M x 36 144M Static random access memory 1.8 or 1.5V 4M x 36 144M Static random access memory 1.8 or 1.5V 16M x 9 144M Static random access memory 1.8 or 1.5V 16M x 9 144M Static random access memory 1.8 or 1.5V 16M x 9 144M Static random access memory 1.8 or 1.5V 16M x 8 144M Static random access memory 1.8 or 1.5V 16M x 8 144M Static random access memory 1.8 or 1.5V 16M x 9 144M Static random access memory 1.8 or 1.5V 8M x 18 144M Static random access memory 1.8 or 1.5V 16M x 9 144M
Maker GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology
organize 4 M x 36 4 M x 36 16MX9 16MX9 16MX9 16MX8 16MX8 16MX9 8MX18 16MX9
Maximum operating temperature + 70 C + 70 C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 85 °C 70 °C
Is it lead-free? - - Lead free Lead free Contains lead Lead free Contains lead Contains lead Contains lead Lead free
Is it Rohs certified? - - conform to conform to incompatible conform to incompatible incompatible incompatible conform to
Parts packaging code - - BGA BGA BGA BGA BGA BGA BGA BGA
package instruction - - LBGA, LBGA, LBGA, LBGA, LBGA, LBGA, LBGA, LBGA,
Contacts - - 165 165 165 165 165 165 165 165
Reach Compliance Code - - compliant compliant compliant compliant compliant compliant compliant compliant
ECCN code - - 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B 3A991.B.2.B
Factory Lead Time - - 12 weeks 12 weeks 12 weeks 12 weeks 12 weeks 12 weeks 12 weeks 12 weeks
Maximum access time - - 0.45 ns 0.45 ns 0.45 ns 0.37 ns 0.37 ns 0.45 ns 0.45 ns 0.37 ns
Other features - - PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE
JESD-30 code - - R-PBGA-B165 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165 R-PBGA-B165
length - - 17 mm 17 mm 17 mm 17 mm 17 mm 17 mm 17 mm 17 mm
memory density - - 150994944 bit 150994944 bit 150994944 bit 134217728 bit 134217728 bit 150994944 bit 150994944 bit 150994944 bit
Memory IC Type - - DDR SRAM DDR SRAM DDR SRAM DDR SRAM DDR SRAM DDR SRAM DDR SRAM DDR SRAM
memory width - - 9 9 9 8 8 9 18 9
Number of functions - - 1 1 1 1 1 1 1 1
Number of terminals - - 165 165 165 165 165 165 165 165
word count - - 16777216 words 16777216 words 16777216 words 16777216 words 16777216 words 16777216 words 8388608 words 16777216 words
character code - - 16000000 16000000 16000000 16000000 16000000 16000000 8000000 16000000
Operating mode - - SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Package body material - - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - - LBGA LBGA LBGA LBGA LBGA LBGA LBGA LBGA
Package shape - - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form - - GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE GRID ARRAY, LOW PROFILE
Parallel/Serial - - PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) - - 260 260 NOT SPECIFIED 260 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 260
Certification status - - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height - - 1.5 mm 1.5 mm 1.5 mm 1.5 mm 1.5 mm 1.5 mm 1.5 mm 1.5 mm
Maximum supply voltage (Vsup) - - 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V
Minimum supply voltage (Vsup) - - 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V
Nominal supply voltage (Vsup) - - 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
surface mount - - YES YES YES YES YES YES YES YES
technology - - CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level - - COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL
Terminal form - - BALL BALL BALL BALL BALL BALL BALL BALL
Terminal pitch - - 1 mm 1 mm 1 mm 1 mm 1 mm 1 mm 1 mm 1 mm
Terminal location - - BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
Maximum time at peak reflow temperature - - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width - - 15 mm 15 mm 15 mm 15 mm 15 mm 15 mm 15 mm 15 mm
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