CY7S1041G
CY7S1041GE
4-Mbit (256K words × 16 bit) Static RAM with
PowerSnooze™ and Error Correcting Code (ECC)
4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
Features
■
High speed
❐
Access time (t
AA
) = 10 ns / 15 ns
Ultra-low power Deep-Sleep (DS) current
❐
I
DS
= 15 µA
Low active and standby currents
❐
Active Current I
CC
= 38-mA typical
❐
Standby Current I
SB2
= 6-mA typical
Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
4.5 V to 5.5 V
Embedded ECC for single-bit error correction
[1]
1.0-V data retention
TTL- compatible inputs and outputs
Error indication (ERR) pin to indicate 1-bit error detection and
correction
Available in Pb-free 44-pin TSOP II, 44-SOJ and 48-ball
VFBGA
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O
0
through I/O
15
) and address pins (A
0
through A
17
) respectively. The Byte High Enable (BHE) and Byte
Low Enable (BLE) inputs control byte writes, and write data on
the corresponding I/O lines to the memory location specified.
BHE controls I/O
8
through I/O
15
and BLE controls I/O
0
through
I/O
7
.
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O
0
through I/O
15
). You can perform byte accesses by asserting the
required byte enable signal (BHE or BLE) to read either the
upper byte or the lower byte of data from the specified address
location
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
The CY7S1041G is available in 44-pin TSOP II, 48-ball VFBGA
and 44-pin (400-mil) Molded SOJ.
■
■
■
■
■
■
■
■
Functional Description
The CY7S1041G is a high-performance PowerSnooze
™
static
RAM organized as 256K words × 16 bits. This device features
fast access times (10 ns) and a unique ultra-low power
Deep-Sleep mode. With Deep-Sleep mode currents as low as
15 µA, the CY7S1041G/ CY7S1041GE devices combine the
best features of fast and low- power SRAMs in industry-standard
package options. The device also features embedded ECC. logic
which can detect and correct single-bit errors in the accessed
location.
Product Portfolio
Power Dissipation
Product
[2]
Range
V
CC
Range (V)
Speed
(ns)
Operating I
CC
,
(mA)
f = f
max
Typ
[3]
Max
40
45
45
–
38
38
Standby, I
SB2
(mA)
Typ
[3]
6
Max
8
Deep-Sleep
current (µA)
Typ
[3]
–
Max
15
CY7S1041G(E)18
CY7S1041G(E)30
CY7S1041G(E)
Industrial
1.65 V–2.2 V
2.2 V–3.6 V
4.5–5.5 V
15
10
10
Notes
1. This device does not support automatic write back on error detection.
2. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer
Ordering Information
for details.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for V
CC
range of 1.65 V – 2.2 V),
V
CC
= 3 V (for V
CC
range of 2.2 V – 3.6 V), and V
CC
= 5 V (for V
CC
range of 4.5 V – 5.5 V), T
A
= 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-92576 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 5, 2018
CY7S1041G
CY7S1041GE
Logic Block Diagram – CY7S1041G / CY7S1041GE
ECC ENCODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INPUT BUFFER
SENSE AMPLIFIERS
ROW DECODER
ECC DECODER
ERR (Optional)
I/O
0
‐I/O
7
I/O
8
‐I/O
15
MEMORY
ARRAY
COLUMN DECODER
A10
A11
A12
A13
A14
A15
A16
A17
BHE
WE
DS
POWER MANAGEMENT
BLOCK
OE
BLE
CE
Document Number: 001-92576 Rev. *G
Page 2 of 22
CY7S1041G
CY7S1041GE
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
Deep-Sleep Mode Characteristics ................................... 9
AC Switching Characteristics ....................................... 10
Switching Waveforms .................................................... 11
Truth Table ...................................................................... 15
ERR Output – CY7S1041GE ........................................... 15
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 001-92576 Rev. *G
Page 3 of 22
CY7S1041G
CY7S1041GE
Pin Configurations
Figure 1. 44-pin TSOP II / 44-SOJ pinout, CY7S1041G
A0
A1
A2
A3
A4
/CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
/OE
/BHE
/BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
/DS
A14
A13
A12
A11
A10
Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Single Chip Enable without ERR, CY7S1041G
[4]
,
Package/Grade ID: BVJXI
[6]
Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Single Chip Enable with ERR, CY7S1041GE
[4, 5]
,
Package/Grade ID: BVJXI
[6]
1
BLE
I/O
8
I/O
9
VSS
VCC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
DS
I/O
0
I/O
2
VCC
VSS
I/O
6
I/O
7
NC
1
A
B
C
D
E
F
G
H
BLE
I/O
8
I/O
9
VSS
VCC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
ERR
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
DS
I/O
0
I/O
2
VCC
VSS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Notes
4. NC pins are not connected internally to the die.
5. ERR is an output pin.
6. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O
[7:0]
and I/O
[15:8]
balls are swapped.
Document Number: 001-92576 Rev. *G
Page 4 of 22
CY7S1041G
CY7S1041GE
Pin Configurations
(continued)
Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Single Chip Enable without ERR, CY7S1041G
[7]
,
Package/Grade ID: BVXI
[9]
Figure 5. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Single Chip Enable with ERR, CY7S1041GE
[7, 8]
,
Package/Grade ID: BVXI
[9]
1
2
OE
BHE
I/O
2
I/O
3
I/O
4
I/O
5
NC
A
8
1
BLE
I/O
0
I/O
1
VSS
VCC
I/O
6
I/O
7
NC
2
OE
BHE
I/O
2
I/O
3
I/O
4
I/O
5
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
10
I/O
11
I/O
12
I/O
13
WE
A
11
6
DS
I/O
8
I/O
9
VCC
VSS
I/O
14
I/O
15
NC
3
A
0
A
3
A
5
A
17
ERR
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
10
I/O
11
I/O
12
I/O
13
WE
A
11
6
DS
I/O
8
I/O
9
VCC
VSS
I/O
14
I/O
15
NC
A
B
C
D
E
F
G
H
BLE
I/O
0
I/O
1
VSS
VCC
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Notes
7. NC pins are not connected internally to the die.
8. ERR is an output pin.
9. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O
[7:0]
and I/O
[15:8]
balls are swapped.
Document Number: 001-92576 Rev. *G
Page 5 of 22
京公网安备 11010802033920号
EEWORLD
