PCA9549
Octal bus switch with individually I
2
C-bus controlled enables
Rev. 02 — 13 July 2009
Product data sheet
1. General description
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled
by the I
2
C-bus. The low ON-state resistance of the switch allows connections to be made
with minimal propagation delay. Any individual A to B channel or combination of channels
can be selected via the I
2
C-bus, determined by the contents of the programmable Control
register. When the I
2
C-bus bit is HIGH (logic 1), the switch is on and data can flow from
Port A to Port B, or vice versa. When the I
2
C-bus bit is LOW (logic 0), the switch is open,
creating a high-impedance state between the two ports, which stops the data flow.
An active LOW reset input (RESET) allows the PCA9549 to recover from a situation
where the I
2
C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I
2
C-bus
state machine and causes all the bits to be open, as does the internal power-on reset
function.
Three address pins allow up to eight devices on the same bus.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
8-bit bus switch (CBT)
5
Ω
switch connection between two ports
I
2
C-bus interface logic; compatible with SMBus standards
Active LOW RESET input
3 address pins allowing up to 8 devices on the I
2
C-bus
Bit selection via I
2
C-bus, in any combination
Power-up with all bits deselected
Low R
on
switches
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: SO24, TSSOP24, HVQFN24
NXP Semiconductors
PCA9549
Octal bus switch with individually I
2
C-bus controlled enables
3. Ordering information
Table 1.
Ordering information
Package
Name
PCA9549D
PCA9549PW
PCA9549BS
SO24
TSSOP24
HVQFN24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
×
4
×
0.85 mm
Version
SOT137-1
SOT355-1
SOT616-1
Type number
3.1 Ordering options
Table 2.
PCA9549D
PCA9549PW
PCA9549BS
Ordering options
Topside mark
PCA9549D
PCA9549
9549
Temperature range
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
Type number
4. Block diagram
PCA9549
1A
2A
3A
4A
5A
6A
7A
8A
1B
2B
3B
4B
5B
6B
7B
8B
V
SS
V
DD
RESET
SWITCH CONTROL LOGIC
RESET
CIRCUIT
SCL
SDA
INPUT
FILTER
I
2
C-BUS
CONTROL
A0
A1
A2
002aaa991
Fig 1.
PCA9549_2
Block diagram
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 July 2009
2 of 25
NXP Semiconductors
PCA9549
Octal bus switch with individually I
2
C-bus controlled enables
5. Pinning information
5.1 Pinning
A0
A1
RESET
1A
1B
2A
2B
3A
3B
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A2
20 8A
19 8B
18 7A
17 7B
16 6A
15 6B
14 5A
13 5B
002aaa992
A0
A1
RESET
1A
1B
2A
2B
3A
3B
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A2
20 8A
19 8B
18 7A
17 7B
16 6A
15 6B
14 5A
13 5B
002aaa993
PCA9549D
PCA9549PW
4A 10
4B 11
V
SS
12
4A 10
4B 11
V
SS
12
Fig 2.
Pin configuration of SO24
24 RESET
Fig 3.
Pin configuration of TSSOP24
20 SDA
23 A1
1A
1B
2A
2B
3A
3B
1
2
3
4
5
6
5B 10
5A 11
6B 12
7
8
9
22 A0
terminal 1
index area
19 SCL
18 A2
17 8A
16 8B
15 7A
14 7B
13 6A
002aaa994
PCA9549BS
4A
4B
Transparent top view
Fig 4.
Pin configuration of HVQFN24 (transparent top view)
PCA9549_2
V
SS
21 V
DD
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 July 2009
3 of 25
NXP Semiconductors
PCA9549
Octal bus switch with individually I
2
C-bus controlled enables
5.2 Pin description
Table 3.
Symbol
A0
A1
RESET
1A
1B
2A
2B
3A
3B
4A
4B
V
SS
5B
5A
6B
6A
7B
7A
8B
8A
A2
SCL
SDA
V
DD
[1]
Pin description
Pin
SO24, TSSOP24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HVQFN24
22
23
24
1
2
3
4
5
6
7
8
9
[1]
10
11
12
13
14
15
16
17
18
19
20
21
address input 0
address input 1
active LOW reset input
input
output
input
output
input
output
input
output
supply ground
output
input
output
input
output
input
output
input
address input 2
serial clock line
serial data line
supply voltage
Description
HVQFN24 package die supply ground is connected to both the V
SS
pin and the exposed center pad. The
V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9549_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 July 2009
4 of 25
NXP Semiconductors
PCA9549
Octal bus switch with individually I
2
C-bus controlled enables
6. Functional description
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9549 is shown in
Figure 5.
To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
1
1
1
0
A2
A1
A0 R/W
fixed
hardware
selectable
002aaa962
Fig 5.
Slave address
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9549, which will be stored in the Control register. If multiple bytes are
received by the PCA9549, it will save the last byte received. This register can be written
and read via the I
2
C-bus.
channel selection bits
(read/write)
7
B7
6
B6
5
B5
4
B4
3
B3
2
B2
1
B1
0
B0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
002aab254
Fig 6.
Control register
6.2.1 Control register definition
One or several bits are selected by the contents of the Control register. This register is
written after the PCA9549 has been addressed. The entire control byte is used to
determine which bit is to be selected. When a bit is selected to close, the bit will close
after the Acknowledge has been placed on the I
2
C-bus.
PCA9549_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 13 July 2009
5 of 25
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