Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Package Information
PACKAGE TYPE: 16 WLP
Package Code
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
JA
)
58°C/W
W161F1+1
21-0491
Refer to
Application Note 1891
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages.
Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated
│
2
MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Electrical Characteristics
(V
BAT
= +1.2V, V
BB1OUT
= +1.8V, V
BB2OUT
= +1.2V, V
L1OUT
= +1.5V, V
L2OUT
= +1.0V, I
BB1OUT
= I
BB2OUT
= I
L1OUT
= I
L2OUT
= 0A,
T
A
= -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at T
A
= +25°C) (Note 1) (Note 2)
PARAMETER
SUPPLY CURRENT
Seal Input Current
KIN
Pullup Resistor to
GND
SYMBOL
I
SEAL
KIN
PULLUP
Buck-boost 1 enabled
CAP Quiescent Current
I
Q_CAP
Buck-boost 1 and 2 enabled
Buck-boost 1 and 2 and LDO 1 enabled
Buck-boost 1 and 2 and LDO 1 and 2 enabled
POWER SEQUENCE
Reset Time Accuracy
BUCK-BOOST REGULATOR
Input Voltage
Output Voltage Range
Quiescent Supply
Current From CAP
Output Accuracy
Power Supply Rejection
Ratio
Maximum Input Power
Maximum Input Current
Short-Circuit Current
Limit
Passive Discharge
Resistance
LDO
Quiescent Supply
Current
Quiescent supply
Current in Dropout
Maximum Output
Current
Output Voltage
I
Q_LDO
I
Q_LDO_D
I
MAX_LDO
V
OUT_LDO
LDO UVLO enabled
Switch mode, V
BB_OUT
= +1.8V
V
BB_OUT
= V
LDO_SET
– 0.1V
(Note 4)
50mV steps
50
0.5
3.65
1.1
0.4
1.7
3.5
2
µA
µA
mA
V
t
RST
V
BAT
V
OUT
Operating
Startup
50mV steps, (Note 3)
Burst mode, no switching, V
BB_OUT
= +1.8V
T
A
= +25°C
V
OUT_ACC_BB_OUT
PSRR
P
IN
I
IN
I
LIM
R
PAS_BB_OUT
T
A
= 0°C to +85°C
T
A
= -40°C to +85°C
C
BB_OUT
= 10µF
(Note 5)
V
BB_OUT
= +1.8V
V
BB_OUT
= +3.3V
Maximum programmable current setting
250
200
244
0.6
10
-1
-1.8
-3
40
-10
0.7
0.8
0.9
1
1
+1.8
+3
dB
mW
mA
A
kΩ
%
+10
2
2
4.05
%
CONDITIONS
Seal mode, all functions disabled,
T
A
= +25°C
MIN
TYP
0.01
465
4
5
5.25
5.5
MAX
0.2
UNITS
µA
kΩ
µA
µA
µA
µA
V
V
µA
I
Q_BB
www.maximintegrated.com
Maxim Integrated
│
3
MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Electrical Characteristics (continued)
(V
BAT
= +1.2V, V
BB1OUT
= +1.8V, V
BB2OUT
= +1.2V, V
L1OUT
= +1.5V, V
L2OUT
= +1.0V, I
BB1OUT
= I
BB2OUT
= I
L1OUT
= I
L2OUT
= 0A,
T
A
= -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at T
A
= +25°C) (Note 1) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
V
BB_OUT
=
(V
LDO_SET
+
0.5V) or higher,
I
LOAD
= 1mA
T
A
= 0°C to +85°C
T
A
= -40°C to +85°C
MIN
-3
-3.5
TYP
MAX
3
%
+3.5
100
-1
0.003
10
V
BB_OUT
= +1.2V
I
LDO_OUT
= 0mA
I
LDO_OUT
= 0mA. Switch mode.
T
J
rising
0.7
2.8
150
21
1
1
mV
%/V
%/mA
kΩ
Ω
V/µs
°C
°C
UNITS
Output Accuracy
V
OUT_ACC_LDO
Dropout Voltage
Line Regulation
Load Regulation
Passive Discharge
Resistance
Power Switch Mode
Resistance
Turn-On Time
Thermal Shutdown
Threshold
Thermal Shutdown
Hysteresis
MONITOR MULTIPLEXER
MON Impedance
Battery Voltage Buffer
Precision
DIGITAL SIGNALS
SDA, SCL, MPC Input
Logic-High
SDA, SCL, MPC Input
Logic-Low
SDA,
RST, KOUT
Output Logic-Low
MPO Output Logic-Low
SCL Clock Frequency
Bus Free Time Between
a STOP and START
Condition
V
DROP_LDO
LINEREG
LDO
LOADREG
LDO
R
PAS_LDO
R
ON_LS
t
ON_SLOPE
T
SD
T
HYS
V
BB_OUT
= V
LDO_SET
= +1.8V,
I
LOAD
= 50mA
V
BB_OUT
= (V
LDO_SET
+ 0.5V) to
+4.05V
I
LOAD
= 50µA to 50mA
R
MON
V
BAT_OFF
Sense pin voltage > +0.5V
-10
500
10
Ω
mV
V
IH
V
IL
V
OL
V
OL_MPO
f
SCL
t
BUF
I
OL
= 4mA
I
OL
= 4mA to GND
I
OL
= 4mA to BATN
(Note 5)
1.4
0.5
0.4
0.4
0.4
0
1.3
400
V
V
V
V
kHz
µs
www.maximintegrated.com
Maxim Integrated
│
4
MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Electrical Characteristics (continued)
(V
BAT
= +1.2V, V
BB1OUT
= +1.8V, V
BB2OUT
= +1.2V, V
L1OUT
= +1.5V, V
L2OUT
= +1.0V, I
BB1OUT
= I
BB2OUT
= I
L1OUT
= I
L2OUT
= 0A,
T
A
= -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at T
A
= +25°C) (Note 1) (Note 2)
PARAMETER
START Condition
(Repeated) Hold Time
Low Period of SCL
Clock
High Period of SCL
Clock
Setup Time for a
Repeated START
Condition
Data Hold Time
Data Setup Time
Setup Time for STOP
Condition
Note
Note
Note
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
6:
7:
8:
SYMBOL
t
HD:STA
t
LOW
t
HIGH
(Note 6)
CONDITIONS
MIN
0.6
1.3
0.6
TYP
MAX
UNITS
µs
µs
µs
µs
µs
µs
ns
µs
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
(Notes 7, 8)
(Note 7)
0.6
0
100
0.6
All devices are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design.
V
BAT
refers to the voltage across the battery terminals; V
BAT
= V
GND
– V
BATN
.
Output voltage must not exceed V
BB_OUT
- V
BATN
= 5.0V.
Actual value may be limited by the lower of the capability of the source (battery) or the maximum input power of the MAX20310.
Timing must be fast enough to prevent the device from entering sleep mode due to bus low for period > t
SLEEP
.
f
SCL
must meet the minimum clock low time plus the rise/fall times.
The maximum t
HD:DAT
has to be met only if the device does not stretch the low period (t
LOW
) of the SCL signal.
The device internally provides a hold time of at least 100ns for the SDA signal (referred to the V
IH_MIN
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
According to your previous post, the sync signal is input at 10MHz, output at 10MHz, and then the phase and duty cycle are multiplied by 2. It seems that there is a big error. I don't know if my confi...
I would like to ask if any brother has used 9261/9263+WINCE5.0. I just came to a new company and used 9263 to develop products. I plan to use the WINCE operating system. The company bought an EBD9261 ...
I recently bought a set of positioning boards and planned to check the RSSI reading. It should be the RSSI between the blind node and the anchor point, but the mobile blind node did not respond, while...
When writing code, a small module uses a 38 decoder, but there is a problem and it cannot pass the syntax check. I looked at it for a long time but couldn't figure out what the problem is. The code is...
I use JLINK to download the program to SDRAM for debugging in IAR environment, but I cannot set breakpoints. The instructions that should jump are executed sequentially. What is the reason? [img]http:...
[backcolor=white][size=3]The example seen on the official website is for MSP430G2553, and the program is as follows: //****************************************************************************** //...
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
