CYWT1543AV18
CYWT1545AV18
72-Mbit QDR
®
II+ SRAM Four-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
■
Configurations
With Read Cycle Latency of 2.0 cycles:
CYWT1543AV18 – 4M x 18
CYWT1545AV18 – 2M x 36
Separate independent read and write data ports
❐
Supports concurrent transactions
250-MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 500 MHz) at 250 MHz
Available in 2.0 clock cycle latency
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
Available in x18 and x36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8 V ± 0.1 V; I/O V
DDQ
= 1.4 V to V
DD [1]
HSTL inputs and variable drive HSTL output buffers
Available in 165-pin CCGA package (21 x 25 x 2.89 mm)
Offered with 0.51 mm Sn/Pb solder columns
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
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Functional Description
The CYWT1543AV18 and CYWT1545AV18 are 1.8 V
synchronous pipelined SRAMs, equipped with QDR II+ archi-
tecture. Similar to QDR II architecture, QDR II+ SRAMs consists
of two separate ports: the read port and the write port to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR II+ architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn around” the data bus that exists with common
I/O devices. Each port is accessed through a common address
bus. Addresses for read and write addresses are latched on
alternate rising edges of the input (K) clock. Accesses to the
QDR II+ read and write ports are completely independent of one
another. To maximize data throughput, both read and write ports
are equipped with DDR interfaces. Each address location is
associated with four 18-bit words (CYWT1543AV18) or 36-bit
words (CYWT1545AV18) that burst sequentially into or out of the
device. Because data is transferred into and out of the device on
every rising edge of both input clocks (K and K), memory
bandwidth is maximized while simplifying system design by
eliminating bus “turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
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Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x18
x36
250 MHz
250
1100
1140
Unit
MHz
mA
Note
1. The QDR consortium specification for V
DDQ
is 1.5 V + 0.1 V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
V
DDQ
= 1.4 V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 002-18432 Rev. **
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 23, 2017
CYWT1543AV18
CYWT1545AV18
Logic Block Diagram (CYWT1543AV18)
D
[17:0]
18
Read Add. Decode
Write Add. Decode
A
(19:0)
20
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
20
A
(19:0)
1M x 18 Array
1M x 18 Array
1M x 18 Array
1M x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
DOFF
Read Data Reg.
CQ
72
V
REF
WPS
BWS
[1:0]
36
Control
Logic
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
QVLD
Logic Block Diagram (CYWT1545AV18)
D
[35:0]
36
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
19
A
(18:0)
512K x 36 Array
512K x 36 Array
512K x 36 Array
512K x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
DOFF
Read Data Reg.
CQ
144
V
REF
WPS
BWS
[3:0]
72
Control
Logic
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
QVLD
Document Number: 002-18432 Rev. **
Page 2 of 26
CYWT1543AV18
CYWT1545AV18
Contents
Pin Configuration ............................................................. 4
165-Pin CCGA (21 x 25x 2.89 mm) Pinout ................. 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 7
Read Operations ......................................................... 7
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 8
Programmable Impedance .......................................... 8
Echo Clocks ................................................................ 8
Valid Data Indicator (QVLD) ........................................ 8
DLL .............................................................................. 8
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ................................................. 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port—Test Clock ................................... 11
Test Mode Select (TMS) ........................................... 11
Test Data-In (TDI) ..................................................... 11
Test Data-Out (TDO) ................................................. 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions .................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 16
Boundary Scan Order .................................................... 17
Power Up Sequence in QDR II+ SRAM ......................... 18
Power Up Sequence ................................................. 18
DLL Constraints ......................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read/Write/Deselect Sequence ................................ 23
Ordering Information ...................................................... 24
Package Diagram ............................................................ 24
Document History Page ................................................. 25
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC® Solutions ...................................................... 26
Cypress Developer Community ................................. 26
Technical Support ..................................................... 26
Document Number: 002-18432 Rev. **
Page 3 of 26
CYWT1543AV18
CYWT1545AV18
Pin Configuration
The pin configuration for CYWT1543AV18 and CYWT1545AV18 follow.
[2]
165-Pin CCGA (21 x 25x 2.89 mm) Pinout
CYWT1543AV18 (4M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CYWT1545AV18 (2M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
NC/288M
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
A
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
NC/144M
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 002-18432 Rev. **
Page 4 of 26
CYWT1543AV18
CYWT1545AV18
Pin Definitions
Pin Name
D
[x:0]
I/O
Pin Description
Input-
Data Input Signals.
Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CYWT1543AV18
D
[17:0]
CYWT1545AV18
D
[35:0]
Input-
Write Port Select
Active
LOW.
Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
Input-
Byte Write Select 0, 1, 2, and 3
Active LOW.
Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CYWT1543AV18
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CYWT1545AV18
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,
BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Input-
Address Inputs.
Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
4M x 18 (four arrays each of 1M x 18) for CYWT1543AV18 and 2M x 36 (four arrays each of 512K x 36)
for CYWT1545AV18. Therefore, only 20 address inputs are needed to access the entire memory array
of CYWT1543AV18 and 19 address inputs for CYWT1545AV18. These inputs are ignored when the
appropriate port is deselected.
Outputs-
Data Output Signals.
These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q
[x:0]
are automatically tristated.
CYWT1543AV18
Q
[17:0]
CYWT1545AV18
Q
[35:0]
Input-
Read Port Select
Active
LOW.
Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of four sequential transfers.
Valid output
indicator
Input-
Clock
Input-
Clock
Echo Clock
Echo Clock
Input
Valid Output Indicator.
The Q Valid indicates valid output data. QVLD is edge-aligned with CQ and CQ.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
. All accesses are initiated on the rising edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[x:0]
.
Synchronous Echo Clock Outputs.
This is a free-running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the
Switching Characteristics
on page 22.
Synchronous Echo Clock Outputs.
This is a free-running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the
Switching Characteristics
on page 22.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DLL Turn Off
Active
LOW.
Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operation are different from those listed in this data sheet. For normal
operation, this pin can be connected to a pull-up through a 10-k or less pull-up resistor. The device
behaves in QDR I mode when the DLL is turned off. In this mode, the device can be operated at a
frequency of up to 167 MHz with QDR I timing.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
Page 5 of 26
WPS
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A
Q
[x:0]
RPS
QVLD
K
K
CQ
CQ
ZQ
DOFF
Input
TDO
TCK
TDI
Output
Input
Input
Document Number: 002-18432 Rev. **
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