AT25SF081-SSHF-B datasheet, PDF

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AT25SF081-SSHF-B: DescriptionNOR Flash 8Mb, 2.5V, 70Mhz Serial Flash; Categorysemiconductor Memory IC NOR flash memory; File Size3MB，47 Pages; ManufacturerAdesto Technologies; Environmental Compliance

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AT25SF081-SSHF-B Overview

NOR Flash 8Mb, 2.5V, 70Mhz Serial Flash

AT25SF081-SSHF-B Parametric

Parameter Name	Attribute value
Maker	Adesto Technologies
Product Category	NOR flash memory
Installation style	SMD/SMT
Package/box	SOIC-8
series	AT25SF081
storage	8 Mbit
maximum clock frequency	104 MHz
Interface Type	SPI
Timing type	Synchronous
Supply voltage - min.	2.3 V
Supply voltage - max.	3.6 V
Supply current—max.	12 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 85 C
Encapsulation	Tube
storage type	Flash
speed	70 MHz
Factory packaging quantity	98

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AT25SF081

8-Mbit, 2.3V Minimum

SPI Serial Flash Memory with Dual-I/O and Quad-IO Support

Features



Single 2.3V - 3.6V Supply



Serial Peripheral Interface (SPI) Compatible

Supports SPI Modes 0 and 3

Supports Dual and Quad Output Read



104MHz Maximum Operating Frequency



Clock-to-Output (t

) of 6 ns



Flexible, Optimized Erase Architecture for Code + Data Storage Applications



Uniform 4-Kbyte Block Erase



Uniform 32-Kbyte Block Erase



Uniform 64-Kbyte Block Erase



Full Chip Erase



Hardware Controlled Locking of Protected Blocks via WP Pin



3 Protected Programmable Security Register Pages



Flexible Programming

Byte/Page Program (1 to 256 Bytes)



Fast Program and Erase Times



0.7ms Typical Page Program (256 Bytes) Time



70ms Typical 4-Kbyte Block Erase Time



300ms Typical 32-Kbyte Block Erase Time



600ms Typical 64-Kbyte Block Erase Time



JEDEC Standard Manufacturer and Device ID Read Methodology



Low Power Dissipation

2µA Deep Power-Down Current (Typical)

10µA Standby current (Typical)

4mA Active Read Current (Typical)



Endurance: 100,000 Program/Erase Cycles



Data Retention: 20 Years



Complies with Full Industrial Temperature Range



Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options



8-lead SOIC (150-mil and 208-mil)

8-pad Ultra Thin DFN (5 x 6 x 0.6 mm and 2 x 3 x 0.6 mm)

8-lead TSSOP (4 x 4 mm)

Die in Wafer Form

DS-25SF081–045I–8/2017

Description

The Adesto

AT25SF081 is a serial interface Flash memory device designed for use in a wide variety of high-volume

consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM

for execution. The flexible erase architecture of the AT25SF081 is ideal for data storage as well, eliminating the need for

additional data storage devices.

The erase block sizes of the AT25SF081 have been optimized to meet the needs of today's code and data storage

applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because

certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and

unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased

memory space efficiency allows additional code routines and data storage segments to be added while still maintaining

the same overall device density.

The device also contains three pages of Security Register that can be used for purposes such as unique device

serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register

pages can be individually locked.

Pin Descriptions and Pinouts

Pin Descriptions

Name and Function

CHIP SELECT:

Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in standby mode (not Deep Power-Down

mode), and the SO pin will be in a high-impedance state. When the device is deselected,

data will not be accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation

such as a program or erase cycle, the device will not enter the standby mode until the

completion of the operation.

SERIAL CLOCK:

This pin is used to provide a clock to the device and is used to control the

flow of data to and from the device. Command, address, and input data present on the SI pin

is always latched in on the rising edge of SCK, while output data on the SO pin is always

clocked out on the falling edge of SCK.

SERIAL INPUT:

The SI pin is used to shift data into the device. The SI pin is used for all data

input including command and address sequences. Data on the SI pin is always latched in on

the rising edge of SCK.

With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin

(I/O

) in conjunction with other pins to allow two or four bits of data on (I/O

3-0

) to be clocked

in on every falling edge of SCK

To maintain consistency with the SPI nomenclature, the SI (I/O

) pin will be referenced as

the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it

will be referenced as I/O

Data present on the SI pin will be ignored whenever the device is deselected (CS is

deasserted).

Asserted

State

Type

Table 1-1.

Symbol

Low

Input

SCK

Input

SI (I/O

)

Input/Output

AT25SF081

DS-25SF081–045I–8/2017

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