PIC18(L)F2X/4X/5XK42
Highly Integrated 8-Bit PIC
®
Microcontrollers in 28- to 48- Pins
Description
The PIC18(L)F2X/4X/5XK42 microcontroller family is available in 28/40/44/48-pin devices. This family features a 12-bit
ADC with Computation (ADC
2
) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing,
averaging, filtering, oversampling and threshold comparison. Additionally, Vectored Interrupt Controller with fixed
latency for handling interrupts, System Bus Arbiter, Direct Memory Access capabilities, UART with support for
Asynchronous, DMX, DALI and LIN protocols, SPI, I
2
C, memory features like Memory Access Partition (MAP) to support
customers in data protection and bootloader applications, Device Information Area (DIA) which stores factory calibration
values to help improve temperature sensor accuracy.
Core Features
• C Compiler Optimized RISC Architecture
• Operating Speed:
- Up to 64 MHz clock input
- 62.5 ns minimum instruction cycle
• Two Direct Memory Access (DMA) Controllers:
- Data transfers to SFR/GPR spaces from
either Program Flash Memory, Data
EEPROM or SFR/GPR spaces
- User programmable source and destination
sizes
- Hardware and software triggered data
transfers
• Vectored Interrupt Capability:
- Selectable high/low priority
- Fixed Interrupt latency
- Programmable vector table base address
• 31-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-Out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
- Variable prescaler selection
- Variable window size selection
- Configurable in hardware or software
• Programmable Code Protection:
- Configurable Boot and App region sizes
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC18LF2X/4X/5XK42)
- 2.3V to 5.5V (PIC18F2X/4X/5XK42)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Power-Saving Functionality
• DOZE mode: Ability to run CPU core slower than
the system clock
• IDLE mode: Ability to halt CPU core while internal
peripherals continue operating
• Sleep mode: Lowest power consumption
• Peripheral Module Disable (PMD):
- Ability to disable peripherals to minimize power
consumption
eXtreme Low-Power (XLP) Features
•
•
•
•
Sleep mode: 50 nA @ 1.8V, typical
Watchdog Timer: 500 nA @ 1.8V, typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
- 8 uA @ 32 kHz, 1.8V, typical
- 32 uA/MHz @ 1.8V, typical
Digital Peripherals
• Three 8-Bit Timers (TMR2/4/6) with Hardware
Limit Timer (HLT)
• Four 16-Bit Timers (TMR0/1/3/5)
• Four Configurable Logic Cell (CLC):
- Integrated combinational and sequential logic
• Three Complementary Waveform Generators
(CWGs):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
- Programmable dead band
- Fault-shutdown input
• Four 16-Bit Capture/Compare/16-Bit PWM (CCP)
modules
• Four 10-bit Pulse Width Modulators (PWMs)
Memory
Up to 128 KB Flash Program Memory
Up to 8 KB Data SRAM Memory
Up to 1 KB Data EEPROM
Memory Access Partition (MAP):
- Bootloader write-protect
- Configurable partition
• Device Information Area (DIA) Stores:
- Temp sensor factory calibrated data
- Fixed Voltage Reference
- Device ID
•
•
•
•
2016 Microchip Technology Inc.
Advance Information
DS40001861B-page 1
PIC18(L)F2X/4X/5XK42
Digital Peripherals (Continued)
• Numerically Controlled Oscillator (NCO):
- Generates true linear frequency control and
increased frequency resolution
- Input Clock: 0 Hz < f
NCO
< 64 MHz
- Resolution: f
NCO
/220
• DSM: Data Signal Modulator:
- Multiplex two carrier clocks, with glitch
prevention feature
- Multiple sources for each carrier
• Programmable CRC with Memory Scan:
- Reliable data/program memory monitoring for
fail-safe operation (e.g., Class B)
- Calculate CRC over any portion of Flash
• Two UART Modules:
- Asynchronous UART, RS-232, RS-485 com-
patible.
- One of the UART modules supports LIN mas-
ter and slave, DMX mode, DALI gear and
device protocols
- Automatic and user timed BREAK period
generation
- DMA compatible
- Automatic checksums
- Programmable 1, 1.5, and 2 Stop bits
- Wake-up on BREAK reception
• One SPI module:
- Configurable length bytes
- Arbitrary length data packets
- Receive-without-transmit option
- Transmit-without-receive option
- Transfer byte counter
- Separate transmit and receive buffers with
2-byte FIFO and DMA capabilities
• Two I
2
C modules, SMBus, PMBus™ compatible:
- Dedicated address, transmit and receive
buffers
- Bus collision detection with arbitration
- Bus time-out detection and handling
- I
2
C, SMBus 2.0 and SMBus 3.0, and 1.8V
input level selections
- Multi-Master mode, including self-addressing
• Device I/O Port Features:
- 25 I/O pins (PIC18(L)F24/25/26/27K42)
- 36 I/O pins (PIC18(L)F45/46/47K42)
- 44 I/O pins (PIC18(L)F55/56/57K42)
- One input-only pin
- Individually programmable I/O direction,
controlled current, open-drain, slew rate,
weak pull-up control
- Interrupt-on-change
- Three external interrupt pins
• Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
• Signal Measurement Timer (SMT):
- 24-bit timer/counter with prescaler
Analog Peripherals
• Analog-to-Digital Converter with Computation
(ADC
2
):
- 12-bit with up to 43 external channels
- Automated post-processing
- Automates math functions on input signals:
averaging, filter calculations, oversampling
and threshold comparison
- Operates in Sleep
- Temperature Sensor
- Internal connection to ADC
- Can be calibrated for improved accuracy
- Hardware Capacitive Voltage Divider (CVD):
- Automates touch sampling and reduces
software size and CPU usage when touch
or proximity sensing is required
- Adjustable sample and hold capacitor array
- Two guard ring output drives
• Two Comparators:
- Comparator Hysteresis enable
- Invert output polarity
- Comparator outputs externally accessible
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Unbuffered I/O pin output
- Internal connections to ADCs and compara-
tors
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
- Connection to ADC, Comp and DAC
Flexible Oscillator Structure
• High-Precision Internal Oscillator:
- Selectable frequency range up to 64 MHz
- Safe clock switching while running
- ±1% at calibration (nominal)
• Low-Power Internal 32 kHz Oscillator
(LFINTOSC)
• External 32 kHz Crystal Oscillator
• External Oscillator Block with:
- x4 PLL with external sources
- Three crystal/resonator modes up to 20 MHz
- Three external clock modes up to 20 MHz
• Fail-Safe Clock Monitor
- Allows for safe shutdown if peripherals clock
stops
• Oscillator Start-up Timer (OST)
- Ensures stability of crystal oscillator sources
DS40001861B-page 2
Advance Information
2016 Microchip Technology Inc.
Direct Memory Access (DMA)
(channels)
Program Flash Memory (KB)
UART/UART with LIN, DMX,
DALI Protocol Support
Signal Measurement Timer
(SMT)
Peripheral Module Disable
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Memory Access Partition
Window Watchdog Timer
(WWDT)
Peripheral Pin Select
Vectored Interrupts
Data SRAM (bytes)
Zero-Cross Detect
Data EEPROM (B)
Data Sheet Index
8-bit/16-bit Timer
CCP/10-bit PWM
2016 Microchip Technology Inc.
TABLE 1:
PIC18(L)F2X/4X/5XK42 FAMILY TYPES
Comparator
12-bit ADC
2
(ch)
5-bit DAC
Device
PIC18(L)F24K42
A
A
B
C
B
B
C
B
B
C
16
32
64
128
32
64
128
32
64
128
256
256
1024
1024
256
1024
1024
1024
1024
1024
1024
2048
4096
8192
2048
4096
8192
2048
4096
8192
25
25
25
25
36
36
36
44
44
44
24
24
24
24
35
35
35
43
43
43
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4/4
4/4
4/4
4/4
4/4
4/4
4/4
4/4
4/4
4/4
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
PIC18(L)F25K42
PIC18(L)F26K42
PIC18(L)F27K42
PIC18(L)F45K42
PIC18(L)F46K42
PIC18(L)F47K42
PIC18(L)F55K42
PIC18(L)F56K42
PIC18(L)F57K42
Note 1:
Data Sheet Index:
A:
B:
C:
Debug
(1)
I
I
I
I
I
I/OPins
I
2
C/SPI
CWG
NCO
CLC
Advance Information
DS40001861B-page 3
PIC18(L)F2X/4X/5XK42
I
I
I
I
I
I – Debugging integrated on chip.
Future Release
Future Release
Future Release
PIC18(L)F24/44K42 Data Sheet, 28-Pin
PIC18(L)F26/45/55/46/56K42 Data Sheet, 48-Pin
PIC18(L)F27/47/57K42 Data Sheet, 48-Pin
Note:
For other small form-factor package availability and marking information, please visit
www.microchip.com/packaging
or contact your local sales office.
PIC18(L)F2X/4X/5XK42
TABLE 2:
Device
PIC18(L)F24K42
PIC18(L)F25K42
PIC18(L)F26K42
PIC18(L)F27K42
PIC18(L)F45K42
PIC18(L)F46K42
PIC18(L)F47K42
PIC18(L)F55K42
PIC18(L)F56K42
PIC18(L)F57K42
Note:
PACKAGES
(S)PDIP
X
X
X
X
X
X
X
X
X
X
SOIC
X
X
X
X
—
—
—
—
—
—
SSOP
X
X
X
X
—
—
—
—
—
—
UQFN
(4x4)
X
X
X
—
—
—
—
—
—
—
QFN
(6x6)
X
X
—
X
—
—
—
—
—
—
TQFP
—
—
—
—
X
X
X
X
X
X
QFN
(8x8)
—
—
—
—
X
X
X
X
X
X
UQFN
(5x5)
—
—
—
—
X
X
X
—
—
—
UQFN
(6x6)
—
—
—
—
—
—
—
X
X
X
Pin details are subject to change.
DS40001861B-page 4
Advance Information
2016 Microchip Technology Inc.
PIC18(L)F2X/4X/5XK42
PIN DIAGRAMS
FIGURE 1:
28-PIN SPDIP, SOIC, SSOP FOR PIC18(L)F2XK42
V
PP
/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
RC0
RC1
RC2
RC3
Note:
1
2
3
4
6
7
8
9
10
11
12
13
14
PIC18(L)F2XK42
5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
RC6
RC5
RC4
See
Table 3
for location of all peripheral functions.
FIGURE 2:
28-PIN UQFN (4X4) FOR PIC18(L)F2XK42
RA1
RA0
RE3/MCLR/V
PP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
28
27
26
25
24
23
22
Note:
See
Table 3
or the pin allocation tables.
2016 Microchip Technology Inc.
Advance Information
RC0
RC1
RC2
RC3
RC4
RC5
RC6
8
9
10
11
12
13
14
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
1
2
3
4
5
6
7
21
20
19
PIC18(L)F2XK42
18
17
16
15
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
DS40001861B-page 5
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