S25FL128S/S25FL256S
128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)
3.0V SPI Flash Memory
Features
CMOS 3.0 Volt Core with Versatile I/O
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 24- or 32-bit address options
– Serial Command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad
DDR
– AutoBoot - power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
– Common Flash Interface (CFI) data for configuration
information.
Programming (1.5 Mbytes/s)
– 256 or 512 Byte Page Programming buffer options
– Quad-Input Page Programming (QPP) for slow clock
systems
– Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase (0.5 to 0.65 Mbytes/s)
– Hybrid sector size option - physical set of thirty two 4-kbyte
sectors at top or bottom of address space with all
remaining sectors of 64 kbytes, for compatibility with prior
generation S25FL devices
– Uniform sector option - always erase 256-kbyte blocks for
software compatibility with higher density and future
devices.
Cycling Endurance
– 100,000 Program-Erase Cycles, minimum
Data Retention
– 20 Year Data Retention, minimum
Security features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against
program or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
Cypress
®
65 nm MirrorBit
®
Technology with Eclipse
™
Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
– SO16 and FBGA packages
Temperature Range / Grade:
– Industrial (-40°C to +85°C)
– Industrial Plus (-40°C to +105°C)
– Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
– Automotive AEC-Q100 Grade 2 (-40°C to +105°C)
– Automotive AEC-Q100 Grade 1 (-40°C to +125°C)
Packages (all Pb-free)
– 16-lead SOIC (300 mil)
– WSON 6 x 8 mm
– BGA-24 6 x 8 mm
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint
options
– Known Good Die and Known Tested Die
Logic Block Diagram
CS#
SCK
SI/IO0
SO/IO1
I/O
WP#/IO2
HOLD#/IO3
RESET#
Data Path
Control
Logic
X Decoders
SRAM
MirrorBit Array
Y Decoders
Data Latch
Cypress Semiconductor Corporation
Document Number: 001-98283 Rev. *O
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 21, 2018
S25FL128S/S25FL256S
Contents
1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
4.3
4.4
4.5
5.
5.1
5.2
5.3
5.4
5.5
6.
6.1
6.2
6.3
6.4
7.
7.1
7.2
7.3
Overview
.......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
5
7
8
7.4
7.5
8.
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
OTP Address Space ..................................................... 48
Registers....................................................................... 50
Data Protection
........................................................... 61
Secure Silicon Region (OTP)........................................ 61
Write Enable Command................................................ 61
Block Protection ............................................................ 62
Advanced Sector Protection ......................................... 63
Commands
.................................................................. 67
Command Set Summary............................................... 68
Identification Commands .............................................. 74
Register Access Commands......................................... 76
Read Memory Array Commands .................................. 87
Program Flash Array Commands ............................... 103
Erase Flash Array Commands.................................... 109
One Time Program Array Commands ........................ 114
Advanced Sector Protection Commands .................... 116
Reset Commands ....................................................... 122
Embedded Algorithm Performance Tables ................. 123
Hardware Interface
Signal Descriptions
..................................................... 9
Input/Output Summary................................................... 9
Address and Data Configuration.................................. 10
RESET# ....................................................................... 10
Serial Clock (SCK) ....................................................... 10
Chip Select (CS#) ........................................................ 10
Serial Input (SI) / IO0 ................................................... 11
Serial Output (SO) / IO1............................................... 11
Write Protect (WP#) / IO2 ............................................ 11
Hold (HOLD#) / IO3 ..................................................... 11
Core Voltage Supply (V
CC
) .......................................... 12
Versatile I/O Power Supply (V
IO
) ................................. 12
Supply and Signal Ground (V
SS
) ................................. 12
Not Connected (NC) .................................................... 12
Reserved for Future Use (RFU)................................... 12
Do Not Use (DNU) ....................................................... 12
Block Diagrams............................................................ 13
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Thermal Resistance .....................................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics ..............................................
Physical Interface
......................................................
SOIC 16-Lead Package ...............................................
WSON Package...........................................................
FAB024 24-Ball BGA Package ....................................
FAC024 24-Ball BGA Package ....................................
Address Space Maps.................................................
Overview ......................................................................
Flash Memory Array.....................................................
ID-CFI Address Space .................................................
14
14
15
19
23
23
24
24
24
24
26
27
29
29
30
31
33
37
39
39
41
42
44
46
46
46
48
10. Data Integrity
............................................................. 125
10.1 Erase Endurance ........................................................ 125
10.2 Data Retention ............................................................ 125
11. Software Interface Reference
.................................. 126
11.1 Command Summary ................................................... 126
11.2 Device ID and Common Flash Interface (ID-CFI) Address
Map............................................................................. 128
11.3 Device ID and Common Flash Interface (ID-CFI) ASO Map
— Automotive Only ..................................................... 142
11.4 Registers..................................................................... 142
11.5 Initial Delivery State .................................................... 145
12.
13.
Ordering Information
................................................ 146
Contacting Cypress
.................................................. 148
14. Revision History........................................................
149
Sales, Solutions, and Legal Information ........................ 154
Worldwide Sales and Design Support ......................... 154
Products ...................................................................... 154
PSoC® Solutions ........................................................ 154
Cypress Developer Community ................................... 154
Technical Support ....................................................... 154
Software Interface
Document Number: 001-98283 Rev. *O
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154
S25FL128S/S25FL256S
1. Overview
1.1
General Description
The Cypress S25FL128S and S25FL256S devices are flash non-volatile memory products using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
This family of devices connect to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and
output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands.
This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for Double Data Rate (DDR)
read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to
be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase
algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface,
asynchronous, NOR flash memories while reducing signal count dramatically.
The S25FL128S and S25FL256S products offer high densities coupled with the flexibility and fast performance required by a variety
of embedded applications. They are ideal for code shadowing, XIP, and data storage.
Document Number: 001-98283 Rev. *O
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