Evaluation Board for
2.7 GHz DDS-Based
AgileRF
™
Synthesizer
AD9956/PCB
EVALUATION BOARD FUNCTIONAL BLOCK DIAGRAM
J7
AD9956
REFCLK
J1
RF
DIVIDER
÷R
SYSCLK
DAC IOUT
DAC IOUT
DDS
LPF
J6
REFCLK
SYSCLK
PLL_OSC
CML DRIVER
DRV_OUT
J5
DRV_OUT
50Ω
J4
PHASE FREQUENCY DETECTOR/
CHARGE PUMP
J2
÷M
PLL_REF
CP_OUT
VCO
LPF
J16
J3
÷N
PLL_OSC
VCO AND LOOP FILTER ONLY POPULATED ON
AD9956-VCO/PCB. THESE SOCKETS LEFT VACANT
FOR USER TO POPULATE ON AD9956/PCB
Figure 1.
DESCRIPTION
This data sheet describes the AD9956/PCB evaluation board
hardware and software. The current version of software
provides a graphical user interface (GUI) that allows easy
communication with the many on-chip functions of the device.
The AD9956 is a highly sophisticated
AgileRF
synthesizer with
numerous user-programmable functions. See the AD9956 data
sheet for detailed information about the part.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
05278-001
AD9956/PCB
TABLE OF CONTENTS
Hardware ........................................................................................... 3
System Requirements................................................................... 3
Setup............................................................................................... 3
Software ............................................................................................. 4
Setup............................................................................................... 4
Running and Using the Software................................................ 4
Control Dialog Box ...................................................................... 5
Profile Dialog Box ........................................................................ 6
Clock Driver Control, Phase-Frequency Detector & Charge
Pump Dialog Box ..........................................................................7
DUT Signals Dialog Box ..............................................................8
DUT I/O Dialog Box ....................................................................8
Debug Window..............................................................................9
Ordering Information.................................................................... 10
Ordering Guide .......................................................................... 10
ESD Caution................................................................................ 10
REVISION HISTORY
1/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
AD9956/PCB
HARDWARE
SYSTEM REQUIREMENTS
To use the evaluation board and run the software, you need
the minimum system requirements listed in Table 1 on the
evaluation PC.
Table 1. System Requirements
Item
Operating System
Processor
Memory
Ports
Clocking
Requirement
Windows® 95 or greater
Pentium® I or better
128 MB or better
One USB port
Signal generator capable of generating
sine waves of at least 3 dBm power, up to
at least 10 MHz
Capability to generate at least 3 inde-
pendent dc voltages
Appropriate measurement device, such
as a spectrum analyzer or a high
bandwidth oscilloscope
When using the part in this kind of application, the external
signal should be applied to the DUT REF IN connector, J2. This
leads to the AD9956 Pins PLLREF/PLLREF, the reference input
of the AD9956’s phase frequency detector. See the AD9956 data
sheet for details on the maximum input speeds and input
sensitivities of these two inputs.
Communicating with the Part
Two interface standards are available on the AD9956/PCB
evaluation board:
•
•
USB 2.0 interface
Header row (U9, U12), which places the part under the
control of an external controller (such as a µP, an FPGA,
or a DSP)
Power Supplies
Measurement
Analog Devices offers a GUI for the PC; it does not offer
control software for external controllers.
Use the jumper settings listed in Table 3 to enable different
modes of communication.
Table 3. Jumper Settings for Communication Modes
Mode
PC control, USB port
External control
Settings
Set W4 to PC. Place a jumper on W15.
Set W3 to parallel, set W4 to manual,
and remove W15 (or leave it stored as a
shunt).
SETUP
Powering the Part
The AD9956/PCB evaluation board has three power supply
connectors: TB1, J14, and J17. TB1 powers the DDS, the phase
detector, and the PC interface logic. J14 powers the VCO (when
populated). J17 powers the CML output driver. Table 2 shows
the necessary connections and the appropriate biasing voltage.
Table 2. Connections and Biasing Voltage
Connector
TB1
TB1
TB1
TB1
TB1
J14
J17
Pin No.
1
2
3
4
5
Label
VCC
DVDD
GND
DVDD_I/O
AVDD
VCO + 5 V
AVDD_CP
Voltage (V)
3.3
1.8
0
3.3
1.8
5
3.3
Master/Slave Configuration
To allow multiple devices to be driven by a common controller,
the evaluation hardware and software allow master/slave con-
figurations. When a board is configured as a master, it can be
connected directly to the USB port or the parallel port of a PC.
A slave can talk to the evaluation software only through another
AD9956 board, which acts as the master.
To configure two boards for this master/slave relationship,
connect a 26-wire ribbon cable from the master port (U9) of the
master board to the slave port (U12) of the slave board. On the
master board, set all the master/slave jumpers (W5 to W13) to
master. On the slave board, set W5 to W12 to slave. Once the
master/slave configuration is set, the evaluation software can
communicate with both because each of the dialog boxes has
an area for the master board and the slave board.
Clocking the Part
The AD9956 can be configured in multiple ways to put the
device into a variety of different loops. The configuration deter-
mines the device input that serves as the input to the loop. To
clock the RF divider/DDS directly, connect the external clock-
ing signal to the DUT RF IN SMA connector, J1. This input
leads to the REFCLK/REFCLK inputs of the AD9956. In many
closed-loop applications, the VCO supplies this signal.
Rev. 0 | Page 3 of 12
AD9956/PCB
SOFTWARE
SETUP
To install the software on the your PC:
1.
2.
3.
Insert the AD9956/PCB evaluation software CD-ROM into
the CD-ROM drive.
Use Windows Explorer to navigate to the CD-ROM drive.
The folders at the root level are labeled
Datashts,
DDS_Tut, Instruct, Layout, Schematic,
and
Software.
The
Datashts
folder contains the data sheet for the
AD9956.
DDS_Tut
contains the DDS tutorial.
Instruct
contains the evaluation board software and hardware
instructions (this document).
Layout
contains the PCB
layout files for the evaluation board.
Software
contains the
setup.exe
file for the evaluation software and the file
install.pdf.
Read
install.pdf
completely and then follow the instruc-
tions in this file to install the software on your PC.
RUNNING AND USING THE SOFTWARE
To launch the evaluation software:
1.
2.
Find the executable,
AD9956v.exe,
in the following folder:
c:\Program Files\ADI\AD9956 Evaluation Software
Double-click the icon to launch the evaluation software. A
status window similar to Figure 2 appears in the center of
the
AD9956 Evaluation Software
dialog box as progress is
made in loading the evaluation software (a black window
with green text). If the software loads successfully, the text
remains green and the “software up and running” message
is displayed. If the loading fails, the text turns red, and a
message describing the failure is displayed.
4.
Three dialog boxes are automatically loaded:
Control, Profile,
and
DUT Signals.
You can load other dialog boxes from the
View
menu. You can also program the registers of the device
directly from the
Debug Window,
which you can access from
the
View
menu.
At startup, the software searches for the presence of a function-
ing AD9956 evaluation board. If it detects the evaluation board,
a green splash screen appears, as shown in Figure 2. If it fails to
detect a working part, a red error message is displayed.
Figure 2. AD9956/PCB Evaluation Board Software Status Message upon Successful Load
Rev. 0 | Page 4 of 12
05278-002
AD9956/PCB
CONTROL DIALOG BOX
Use the
Control
dialog box to enable and disable individual
device functions, program the input clock speed, and toggle
various other options. Figure 3 shows the sections of the
Control
dialog box:
Clock, Output Waveform, Linear Sweep,
Power Down, Accumulator Control,
and
Sync Multi DUT’s.
Click
Charge Pump/Clock Driver Window, I/O Interface
Window,
or
DUT Signals Window
to access these dialog
boxes.
To bypass the RF divider and pipe the REFCLK input directly to
the DDS core, select
RF Divider RefClk Mux.
Even though the
divider operates at /1, /2, /4, or /8, and this divided signal can be
ported to the PECL driver, the raw, undivided REFCLK is used
as the internal system clock when this box is checked. Do
not
select this box, if the REFCLK input is greater than 400 MHz.
Output Waveform
In the
Output Waveform
box, select either a cosine(x) or a
sine(x) function for the angle-to-amplitude conversion.
LOAD and READ
At the bottom right of the dialog box are the
LOAD
and
READ
buttons.
After you have made changes to the evaluation software, click
LOAD
to send the data to the device. In addition to sending
data, you can also configure
LOAD
to automatically send an
I/O update signal to the DUT when the software finishes
sending data. See the DUT Signals Dialog Box section for
details. When new data is ready to be sent,
LOAD
flashes
green, indicating that a you need to issue a
LOAD.
Click
READ
to perform a readback of the currently program-
med status of the device and to update the GUI with the current
settings.
Linear Sweep
Use the
Linear Sweep
section to enable the linear sweep
functions of the DDS. See the AD9956 data sheet for a detailed
explanation of these modes of operation.
Select
Enable
to turn on the frequency accumulator. If the
No
Dwell
box is not checked, the part is set in ordinary linear
sweep mode.
Select both
Enable
and
No Dwell
to put the part into linear
sweep no-dwell mode.
When you select
Load SRR @ I/O Update,
the current
countdown of the sweep ramp rate is cleared every time an
I/O_UPDATE signal is sent to the part. When using manual
programming through the GUI, it is almost impossible to notice
the effect of this function because the sweep ramp rates cycle
through their countdown timers in less than 655 µs, even when
programmed to a maximum value.
The linear sweep parameters (delta frequencies and ramp rates)
are controlled in the
Linear Sweep
section (see Figure 3). The
sweep itself, however, is controlled by the
Ramp Up
and
Ramp
Down
buttons, which appear at the bottom of the
Profile
dialog
box when the
Linear Sweep Enable
box is checked. See the
Profile Dialog Box section for details.
Power Down
05278-003
In the
Power Down
section, select the check boxes for the
circuit blocks that you want to power down.
Figure 3. Control Dialog Box
Accumulator Control
This section controls the clear functions for the phase and
frequency accumulators.
Select
Auto Clear Frequency Accum.
or
Auto Clear Phase
Accum.
to clear and release the corresponding accumulator.
The auto clear function sets the accumulator to a known value
of 0 and then begins accumulating.
Clock
To program the reference clock and the RF prescalar values:
1.
2.
3.
In the
Ref Clock
box, type the operating frequency of the
external reference clock. The maximum is 2.7 GHz.
In the
Divider Ratio
box, select a divider value for the RF
prescalar. The value must be in the range of 1 and 8.
Click
LOAD.
Rev. 0 | Page 5 of 12
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