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NLVHCT541ADWR2G

Description
Logic gate LOG CMOS BUS INTRFCE
Categorysemiconductor    Logic integrated circuit    Logic gate   
File Size89KB,7 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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NLVHCT541ADWR2G Overview

Logic gate LOG CMOS BUS INTRFCE

NLVHCT541ADWR2G Parametric

Parameter NameAttribute value
MakerON Semiconductor
Product Categorylogic gate
qualificationsAEC-Q100
EncapsulationCut Tape
EncapsulationReel
seriesMC74HCT541A
Factory packaging quantity1000
MC74HCT541A
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver With
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT541A is identical in pinout to the LS541. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to high speed CMOS inputs.
The HCT541A is an octal non−inverting buffer/line driver/line
receiver designed to be used with 3−state memory address drivers,
clock drivers, and other bus−oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active−low output enables.
Features
www.onsemi.com
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
V
CC
OE2 Y1
20 19 18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1
mA
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
A1
A2
A3
A4
A5
A6
A7
A8
Output
Enables
OE1
OE2
2
3
4
5
6
7
8
9
1
19
PIN 20 = V
CC
PIN 10 = GND
1
18
17
16
15
14
13
12
11
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1
2
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND
OE1 A1
MARKING DIAGRAMS
20
HCT541A
AWLYYWWG
1
SOIC−20
1
TSSOP−20
20
HCT
541A
ALYWG
G
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Non-Inverting
Outputs
OE1
L
L
H
X
Inputs
OE2
L
L
X
H
A
L
H
X
X
L
H
Z
Z
Output Y
Data
Inputs
Z = High Impedance
X = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
June, 2017 − Rev. 8
Publication Order Number:
MC74HCT541A/D

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qualifications AEC-Q100 AEC-Q100 AEC-Q100
series MC74HCT541A MC74HCT541A MC74HCT541A
Factory packaging quantity 1000 2500 38
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