IS43LD32800B-25BLI-TR datasheet, PDF

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IS43LD32800B-25BLI-TR: DescriptionDynamic random access memory 256M, 1.2/1.8V, LPDDR2, 8Mx32, 400MHz, 134 ball BGA (10mmx11.5mm) RoHS, IT, T&R; Categorysemiconductor Memory IC Dynamic random access memory; File Size7MB，145 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/; Environmental Compliance

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IS43LD32800B-25BLI-TR Overview

Dynamic random access memory 256M, 1.2/1.8V, LPDDR2, 8Mx32, 400MHz, 134 ball BGA (10mmx11.5mm) RoHS, IT, T&R

IS43LD32800B-25BLI-TR Parametric

Parameter Name	Attribute value
Maker	ISSI(Integrated Silicon Solution Inc.)
Product Category	dynamic random access memory
type	SDRAM Mobile - LPDDR2
Data bus width	32 bit
organize	8 M x 32
Package/box	FBGA-134
storage	256 Mbit
maximum clock frequency	400 MHz
Supply voltage - max.	1.95 V
Supply voltage - min.	1.14 V
Supply current—max.	40 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 85 C
series	IS43LD16160B
Encapsulation	Reel
Installation style	SMD/SMT
Factory packaging quantity	2000

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IS43/46LD16160B

IS43/46LD32800B

256Mb (x16, x32) Mobile LpddR2 s4 sdRAM

FeAtURes

•

Low-voltage Core and I/O Power Supplies

VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V,

VDD1 = 1.70-1.95V

•

High Speed Un-terminated Logic(HSUL_12) I/O

Interface

•

Clock Frequency Range : 10MHz to 533MHz

(data rate range : 20Mbps to 1066Mbps per I/O)

•

Four-bit Pre-fetch DDR Architecture

•

Multiplexed, double data rate, command/ad-

dress inputs

•

Four internal banks for concurrent operation

•

Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

•

Programmable Read/Write latencies(RL/WL)

and burst lengths(4,8 or 16)

•

ZQ Calibration

•

On-chip temperature sensor to control self re-

fresh rate

•

Partial –array self refresh(PASR)

•

Deep power-down mode(DPD)

•

Operation Temperature

Commercial (T

= 0°C to 85°C)

Industrial (T

= -40°C to 85°C)

Automotive, A1 (T

= -40°C to 85°C)

Automotive, A2 (T

= -40°C to 105°C)

descRiption

pReLiMinARY inFoRMAtion

MARcH 2018

The IS43/46LD16160B/32800B is 256Mbit CMOS

LPDDR2 DRAM. The device is organized as 4 banks

of 4Meg words of 16bits or 2Meg words of 32bits.

This product uses a double-data-rate architecture to

achieve high-speed operation. The double data rate

architecture is essentially a 4N prefetch architecture

with an interface designed to transfer two data words

per clock cycle at the I/O pins. This product offers fully

synchronous operations referenced to both rising and

falling edges of the clock. The data paths are internally

pipelined and 4n bits prefetched to achieve very high

bandwidth.

AddRess tABLe

Parameter

Row Addresses

Column Addresses

Bank Addresses

Refresh Count

8Mx32

R0-R12

C0-C7

BA0-BA1

4096

16Mx16

R0-R12

C0-C8

BA0-BA1

4096

keY tiMinG pARAMeteRs

(1)

Speed

Grade

-18

-25

-3

Data

Rate

(Mb/s)

1066

800

667

Write

Read tRCD/

Latency Latency tRP

(2)

Typical

options

•

Configuration:

− 16Mx16 (4M x 16 x 4 banks)

− 8Mx32 (2M x 32 x 4 banks)

Package:

− 134-ball BGA for x16 / x32

− 168-ball PoP BGA for x32

Notes:

1. Other clock frequencies/data rates supported; please

refer to AC timing tables.

2. Please contact ISSI for Fast t

rcd

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-

pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon

Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 0A

02/09/2018

IS43LD32800B-25BLI-TR Related Products

	IS43LD32800B-25BLI-TR	IS43LD16160B-25BLI	IS43LD32800B-25BLI	IS43LD16160B-25BLI-TR
Description	Dynamic random access memory 256M, 1.2/1.8V, LPDDR2, 8Mx32, 400MHz, 134 ball BGA (10mmx11.5mm) RoHS, IT, T&R	Dynamic random access memory 256M, 1.2/1.8V, LPDDR2, 16Mx16, 400MHz, 134 ball BGA (10mmx11.5mm) RoHS, IT	Dynamic random access memory 256M, 1.2/1.8V, LPDDR2, 8Mx32, 400MHz, 134 ball BGA (10mmx11.5mm) RoHS, IT	Dynamic random access memory 256M, 1.2/1.8V, LPDDR2, 16Mx16, 400MHz, 134 ball BGA (10mmx11.5mm) RoHS, IT, T&R
Maker	ISSI(Integrated Silicon Solution Inc.)	ISSI(Integrated Silicon Solution Inc.)	ISSI(Integrated Silicon Solution Inc.)	ISSI(Integrated Silicon Solution Inc.)
Product Category	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory
type	SDRAM Mobile - LPDDR2	SDRAM Mobile - LPDDR2	SDRAM Mobile - LPDDR2	SDRAM Mobile - LPDDR2
Data bus width	32 bit	16 bit	32 bit	16 bit
organize	8 M x 32	16 M x 16	8 M x 32	16 M x 16
Package/box	FBGA-134	FBGA-134	FBGA-134	FBGA-134
storage	256 Mbit	256 Mbit	256 Mbit	256 Mbit
maximum clock frequency	400 MHz	400 MHz	400 MHz	400 MHz
Supply voltage - max.	1.95 V	1.95 V	1.95 V	1.95 V
Supply voltage - min.	1.14 V	1.14 V	1.14 V	1.14 V
Supply current—max.	40 mA	40 mA	40 mA	40 mA
Minimum operating temperature	- 40 C	- 40 C	- 40 C	- 40 C
Maximum operating temperature	+ 85 C	+ 85 C	+ 85 C	+ 85 C
series	IS43LD16160B	IS43LD16160B	IS43LD16160B	IS43LD16160B
Installation style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
Factory packaging quantity	2000	171	171	2000

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