MT46H64M32LFBQ-48 IT:C TR datasheet, PDF

Datasheet> All Categories > semiconductor> Memory IC> Dynamic random access memory> MT46H64M32LFBQ-48 IT:C TR

MT46H64M32LFBQ-48 IT:C TR: DescriptionDynamic Random Access Memory MOBILE DDR 2G 64MX32 FBGA; Categorysemiconductor Memory IC Dynamic random access memory; File Size6MB，99 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

Download Datasheet Parametric View All

MT46H64M32LFBQ-48 IT:C TR Overview

Dynamic Random Access Memory MOBILE DDR 2G 64MX32 FBGA

MT46H64M32LFBQ-48 IT:C TR Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	dynamic random access memory
type	SDRAM Mobile - LPDDR1
Data bus width	32 bit
organize	64 M x 32
Package/box	VFBGA-90
storage	2 Gbit
maximum clock frequency	208 MHz
interview time	4.8 ns
Supply voltage - max.	1.95 V
Supply voltage - min.	1.7 V
Supply current—max.	170 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 85 C
series	MT46H
Encapsulation	Cut Tape
Encapsulation	MouseReel
Encapsulation	Reel
Installation style	SMD/SMT
Factory packaging quantity	1000

Preview

Download Datasheet

View All

2Gb: x16, x32 Automotive LPDDR SDRAM

Features

Automotive LPDDR SDRAM

MT46H128M16LF – 32 Meg x 16 x 4 Banks

MT46H64M32LF – 16 Meg x 32 x 4 Banks

Features

• V

DDQ

= 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data; one mask

per byte

• Programmable burst lengths (BL): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• Temperature-compensated self refresh (TCSR)

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Status read register (SRR)

• Selectable output drive strength (DS)

• Clock stop capability

• 64ms refresh; 32ms for the automotive temperature

range

Table 1: Key Timing Parameters (CL = 3)

Speed Grade

-48

Clock Rate

208 MHz

Access Time

4.8ns

Options

• V

DDQ

– 1.8V/1.8V

• Configuration

– 128 Meg x 16 (32 Meg x 16 x 4 banks)

– 64 Meg x 32 (16 Meg x 32 x 4 banks)

• Addressing

– JEDEC-standard

• Plastic "green" package

– 60-ball VFBGA (8mm x 9mm)

– 90-ball VFBGA (8mm x 13mm)

• Timing – cycle time

– 4.8ns @ CL = 3 (208 MHz)

• Special Options

– Automotive (package-level burn-in)

• Operating temperature range

– From –40˚C to +85˚C

– From –40˚C to +105˚C

• Design revision

Notes:

1. Contact factory for availability.

2. Self refresh supported up to 85 ºC.

Mark

128M16

64M32

-48

Table 2: Configuration Addressing – 2Gb

Architecture

Configuration

Refresh count

Row addressing

Column addressing

128 Meg x 16

32 Meg x 16 x 4 banks

16K A[13:0]

2K A11, A[9:0]

64 Meg x 32

16 Meg x 32 x 4 banks

16K A[13:0]

1K A[9:0]

09005aef8541eee0

t89m_auto_lpddr.pdf - Rev. I 05/18 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x16, x32 Automotive LPDDR SDRAM

Features

Contents

Important Notes and Warnings ......................................................................................................................... 8

General Description ......................................................................................................................................... 8

Functional Block Diagrams ............................................................................................................................. 10

Ball Assignments ............................................................................................................................................ 12

Ball Descriptions ............................................................................................................................................ 14

Package Block Diagrams ................................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 17

Electrical Specifications .................................................................................................................................. 19

Electrical Specifications – I

Parameters ........................................................................................................ 22

Electrical Specifications – AC Operating Conditions ......................................................................................... 28

Output Drive Characteristics ........................................................................................................................... 32

Functional Description ................................................................................................................................... 35

Commands .................................................................................................................................................... 36

DESELECT ................................................................................................................................................. 37

NO OPERATION ......................................................................................................................................... 37

LOAD MODE REGISTER ............................................................................................................................. 37

ACTIVE ...................................................................................................................................................... 37

READ ......................................................................................................................................................... 38

WRITE ....................................................................................................................................................... 39

PRECHARGE .............................................................................................................................................. 40

BURST TERMINATE ................................................................................................................................... 41

AUTO REFRESH ......................................................................................................................................... 41

SELF REFRESH ........................................................................................................................................... 42

DEEP POWER-DOWN ................................................................................................................................. 42

Truth Tables ................................................................................................................................................... 43

State Diagram ................................................................................................................................................ 48

Initialization .................................................................................................................................................. 49

Standard Mode Register .................................................................................................................................. 52

Burst Length .............................................................................................................................................. 53

Burst Type .................................................................................................................................................. 53

CAS Latency ............................................................................................................................................... 54

Operating Mode ......................................................................................................................................... 55

Extended Mode Register ................................................................................................................................. 56

Temperature-Compensated Self Refresh ...................................................................................................... 56

Partial-Array Self Refresh ............................................................................................................................ 57

Output Drive Strength ................................................................................................................................ 57

Status Read Register ....................................................................................................................................... 58

Bank/Row Activation ...................................................................................................................................... 60

READ Operation ............................................................................................................................................. 61

WRITE Operation ........................................................................................................................................... 72

PRECHARGE Operation .................................................................................................................................. 84

Auto Precharge ............................................................................................................................................... 84

Concurrent Auto Precharge ......................................................................................................................... 84

AUTO REFRESH Operation ............................................................................................................................. 90

SELF REFRESH Operation ............................................................................................................................... 91

Power-Down .................................................................................................................................................. 93

Deep Power-Down ..................................................................................................................................... 94

Clock Change Frequency ................................................................................................................................ 96

Revision History ............................................................................................................................................. 97

Rev. I – 05/18 .............................................................................................................................................. 97

09005aef8541eee0

t89m_auto_lpddr.pdf - Rev. I 05/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x16, x32 Automotive LPDDR SDRAM

Features

List of Figures

Figure 1: 2Gb Mobile LPDDR Part Numbering .................................................................................................. 2

Figure 2: Functional Block Diagram (x16) ....................................................................................................... 10

Figure 3: Functional Block Diagram (x32) ....................................................................................................... 11

Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 12

Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 13

Figure 6: Single Rank, Single Channel (1 Die) Package Block Diagram .............................................................. 16

Figure 7: 60-Ball VFBGA (8mm x 9mm), Package Code: DD ............................................................................. 17

Figure 8: 90-Ball VFBGA (8mm x 13mm), Package Code: BQ ............................................................................ 18

Figure 9: Typical Self Refresh Current vs. Temperature .................................................................................... 27

Figure 10: ACTIVE Command ........................................................................................................................ 38

Figure 11: READ Command ........................................................................................................................... 39

Figure 12: WRITE Command ......................................................................................................................... 40

Figure 13: PRECHARGE Command ................................................................................................................ 41

Figure 14: DEEP POWER-DOWN Command ................................................................................................... 42

Figure 15: Simplified State Diagram ............................................................................................................... 48

Figure 16: Initialize and Load Mode Registers ................................................................................................. 50

Figure 17: Alternate Initialization with CKE LOW ............................................................................................ 51

Figure 18: Standard Mode Register Definition ................................................................................................. 52

Figure 19: CAS Latency .................................................................................................................................. 55

Figure 20: Extended Mode Register ................................................................................................................ 56

Figure 21: Status Read Register Timing ........................................................................................................... 58

Figure 22: Status Register Definition .............................................................................................................. 59

Figure 23: READ Burst ................................................................................................................................... 62

Figure 24: Consecutive READ Bursts .............................................................................................................. 63

Figure 25: Nonconsecutive READ Bursts ........................................................................................................ 64

Figure 26: Random Read Accesses .................................................................................................................. 65

Figure 27: Terminating a READ Burst ............................................................................................................. 66

Figure 28: READ-to-WRITE ............................................................................................................................ 67

Figure 29: READ-to-PRECHARGE .................................................................................................................. 68

Figure 30: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x16) .................................................... 69

Figure 31: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x32) .................................................... 70

Figure 32: Data Output Timing –

AC and

DQSCK .......................................................................................... 71

Figure 33: Data Input Timing ......................................................................................................................... 73

Figure 34: Write – DM Operation .................................................................................................................... 74

Figure 35: WRITE Burst ................................................................................................................................. 75

Figure 36: Consecutive WRITE-to-WRITE ....................................................................................................... 76

Figure 37: Nonconsecutive WRITE-to-WRITE ................................................................................................. 76

Figure 38: Random WRITE Cycles .................................................................................................................. 77

Figure 39: WRITE-to-READ – Uninterrupting ................................................................................................. 78

Figure 40: WRITE-to-READ – Interrupting ...................................................................................................... 79

Figure 41: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 80

Figure 42: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 81

Figure 43: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 82

Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 83

Figure 45: Bank Read – With Auto Precharge ................................................................................................... 86

Figure 46: Bank Read – Without Auto Precharge .............................................................................................. 87

Figure 47: Bank Write – With Auto Precharge .................................................................................................. 88

Figure 48: Bank Write – Without Auto Precharge ............................................................................................. 89

Figure 49: Auto Refresh Mode ........................................................................................................................ 90

Figure 50: Self Refresh Mode .......................................................................................................................... 92

09005aef8541eee0

t89m_auto_lpddr.pdf - Rev. I 05/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Recommended Resources

It is forbidden to reconnect the circuit when a call comes after a power outagea

Motor sequential starting and individual stopping control circuit b

Automatic power-off nickel-cadmium battery charger circuit diagram

Basic application circuit diagram

clock pulse coupling circuit

Simplified schematic diagram of delta conversion UPS

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components