W9751G6KB
8M
4 BANKS
16 BIT DDR2 SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
8.1
8.2
GENERAL DESCRIPTION ................................................................................................................... 4
FEATURES ........................................................................................................................................... 4
ORDER INFORMATION ....................................................................................................................... 5
KEY PARAMETERS ............................................................................................................................. 5
BALL CONFIGURATION ...................................................................................................................... 6
BALL DESCRIPTION ............................................................................................................................ 7
BLOCK DIAGRAM ................................................................................................................................ 8
FUNCTIONAL DESCRIPTION .............................................................................................................. 9
Power-up and Initialization Sequence ................................................................................................... 9
Mode Register and Extended Mode Registers Operation ................................................................... 10
8.2.1
Mode Register Set Command (MRS)............................................................................... 10
8.2.2
Extend Mode Register Set Commands (EMRS) .............................................................. 11
8.2.3
Off-Chip Driver (OCD) Impedance Adjustment ................................................................ 15
8.2.4
On-Die Termination (ODT) ............................................................................................... 18
8.2.5
ODT related timings ......................................................................................................... 18
Command Function ............................................................................................................................. 20
8.3.1
Bank Activate Command.................................................................................................. 20
8.3.2
Read Command ............................................................................................................... 20
8.3.3
Write Command ............................................................................................................... 21
8.3.4
Burst Read with Auto-precharge Command..................................................................... 21
8.3.5
Burst Write with Auto-precharge Command ..................................................................... 21
8.3.6
Precharge All Command .................................................................................................. 21
8.3.7
Self Refresh Entry Command .......................................................................................... 21
8.3.8
Self Refresh Exit Command ............................................................................................. 22
8.3.9
Refresh Command ........................................................................................................... 22
8.3.10
No-Operation Command .................................................................................................. 23
8.3.11
Device Deselect Command.............................................................................................. 23
Read and Write access modes ........................................................................................................... 23
8.4.1
Posted
CAS
..................................................................................................................... 23
8.4.2
Burst mode operation ....................................................................................................... 24
8.4.3
Burst read mode operation ............................................................................................... 25
8.4.4
Burst write mode operation .............................................................................................. 25
8.4.5
Write data mask ............................................................................................................... 26
Burst Interrupt ..................................................................................................................................... 26
Precharge operation............................................................................................................................ 27
8.6.1
Burst read operation followed by precharge ..................................................................... 27
8.6.2
Burst write operation followed by precharge .................................................................... 27
Auto-precharge operation ................................................................................................................... 27
8.7.1
Burst read with Auto-precharge ....................................................................................... 28
8.7.2
Burst write with Auto-precharge ....................................................................................... 28
Refresh Operation ............................................................................................................................... 29
Power Down Mode .............................................................................................................................. 29
8.9.1
Power Down Entry ........................................................................................................... 30
8.9.2
Power Down Exit .............................................................................................................. 30
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Publication Release Date: Jan. 23, 2017
Revision: A09
-1-
W9751G6KB
8.10
9.
9.1
9.2
9.3
9.4
9.5
10.
Input clock frequency change during precharge power down ............................................................. 30
OPERATION MODE ........................................................................................................................... 31
Command Truth Table ........................................................................................................................ 31
Clock Enable (CKE) Truth Table for Synchronous Transitions ........................................................... 32
Data Mask (DM) Truth Table ............................................................................................................... 32
Function Truth Table ........................................................................................................................... 33
Simplified Stated Diagram ................................................................................................................... 36
ELECTRICAL CHARACTERISTICS ................................................................................................... 37
10.1 Absolute Maximum Ratings ................................................................................................................ 37
10.2 Operating Temperature Condition ....................................................................................................... 37
10.3 Recommended DC Operating Conditions ........................................................................................... 37
10.4 ODT DC Electrical Characteristics ...................................................................................................... 38
10.5 Input DC Logic Level ........................................................................................................................... 38
10.6 Input AC Logic Level ........................................................................................................................... 38
10.7 Capacitance ........................................................................................................................................ 39
10.8 Leakage and Output Buffer Characteristics ........................................................................................ 39
10.9 DC Characteristics .............................................................................................................................. 40
10.10
IDD Measurement Test Parameters .......................................................................................... 42
10.11
AC Characteristics ..................................................................................................................... 43
10.11.1
AC Characteristics and Operating Condition for -18/18I/18J speed grade ....................... 43
10.11.2
AC Characteristics and Operating Condition for -25/25L/25I/25J/-3 speed grade............ 45
10.12
AC Input Test Conditions ........................................................................................................... 66
10.13
Differential Input/Output AC Logic Levels .................................................................................. 66
10.14
AC Overshoot / Undershoot Specification ................................................................................. 67
10.14.1
AC Overshoot / Undershoot Specification for Address and Control Pins: ........................ 67
10.14.2
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: .......... 67
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
11.23
TIMING WAVEFORMS ....................................................................................................................... 68
Command Input Timing ....................................................................................................................... 68
ODT Timing for Active/Standby Mode ................................................................................................. 69
ODT Timing for Power Down Mode .................................................................................................... 69
ODT Timing mode switch at entering power down mode .................................................................... 70
ODT Timing mode switch at exiting power down mode ...................................................................... 71
Data output (read) timing .................................................................................................................... 72
Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................ 72
Data input (write) timing ...................................................................................................................... 73
Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) .................................................................... 73
Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ...................................... 74
Seamless burst write operation: RL = 5 ( WL = 4, BL = 4) ......................................................... 74
Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) ............................................................. 75
Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) .................................................. 75
Write operation with Data Mask: WL=3, AL=0, BL=4) ............................................................... 76
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) ............ 77
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............ 77
Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) ............ 78
Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) ............ 78
Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ............ 79
Burst write operation followed by precharge: WL = (RL-1) = 3 .................................................. 79
Burst write operation followed by precharge: WL = (RL-1) = 4 .................................................. 80
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............... 80
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ............... 81
11.
Publication Release Date: Jan. 23, 2017
Revision: A09
-2-
W9751G6KB
11.24
Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) ....................................................................................... 81
11.25
Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) ....................................................................................... 82
11.26
Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3 ................................. 82
11.27
Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 ....................... 83
11.28
Self Refresh Timing ................................................................................................................... 83
11.29
Basic Power Down Entry and Exit Timing.................................................................................. 84
11.30
Precharged Power Down Entry and Exit Timing ........................................................................ 84
11.31
Clock frequency change in precharge Power Down mode ........................................................ 85
12.
13.
PACKAGE SPECIFICATION .............................................................................................................. 86
REVISION HISTORY .......................................................................................................................... 87
Publication Release Date: Jan. 23, 2017
Revision: A09
-3-
W9751G6KB
1. GENERAL DESCRIPTION
The W9751G6KB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words
4 banks
16 bits.
This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various
applications. W9751G6KB is sorted into the following speed grades: -18, 18I, 18J, -25, 25L, 25I, 25J
and -3.
The -18, 18I and 18J grade parts are compliant to the DDR2-1066 (7-7-7) specification (the 18I
industrial grade which is guaranteed to support -40°C ≤ T
CASE
≤ 95°C, the 18J industrial plus grade
which is guaranteed to support -40°C ≤ T
CASE
≤ 105°C).
The -25, 25L, 25I and 25J grade parts are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6)
specification (the 25I industrial grade which is guaranteed to support -40°C ≤ T
CASE
≤ 95°C, the 25J
industrial plus grade which is guaranteed to support -40°C ≤ T
CASE
≤ 105°C).
The -3 grade parts is compliant to the DDR2-667 (5-5-5) specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and
CLK
falling). All
I/Os are synchronized with a single ended DQS or differential DQS-
DQS
pair in a source
synchronous fashion.
2. FEATURES
Power Supply: V
DD
, V
DDQ
= 1.8 V ± 0.1V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and
DQS
) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and
CLK
)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted
CAS
programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8X12.5 mm
2
), using Lead free materials with RoHS compliant
Publication Release Date: Jan. 23, 2017
Revision: A09
-4-
W9751G6KB
3. ORDER INFORMATION
PART NUMBER
SPEED GRADE
OPERATING TEMPERATURE
W9751G6KB-18
W9751G6KB18I
W9751G6KB18J
W9751G6KB-25
W9751G6KB25L
W9751G6KB25I
W9751G6KB25J
W9751G6KB-3
DDR2-1066 (7-7-7)
DDR2-1066 (7-7-7)
DDR2-1066 (7-7-7)
DDR2-800 (5-5-5) or DDR2-800 (6-6-6)
DDR2-800 (5-5-5) or DDR2-800 (6-6-6)
DDR2-800 (5-5-5) or DDR2-800 (6-6-6)
DDR2-800 (5-5-5) or DDR2-800 (6-6-6)
DDR2-667 (5-5-5)
0°C ≤ T
CASE
≤ 85°C
-40°C ≤ T
CASE
≤ 95°C
-40°C ≤ T
CASE
≤ 105°C
0°C ≤ T
CASE
≤ 85°C
0°C ≤ T
CASE
≤ 85°C
-40°C ≤ T
CASE
≤ 95°C
-40°C ≤ T
CASE
≤ 105°C
0°C ≤ T
CASE
≤ 85°C
4. KEY PARAMETERS
SPEED GRADE
SYM.
Bin(CL-t
RCD
-t
RP
)
Part Number Extension
@CL = 7
@CL = 6
t
CK(avg)
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
DDR2-1066
7-7-7
-18/18I/18J
1.875 nS
7.5 nS
2.5 nS
7.5 nS
3 nS
7.5 nS
3.75 nS
7.5 nS
13.125 nS
7.8 μS*
2, 3
Max.
7.8 μS*
1
3.9 μS*
4
3.9 μS*
4
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
13.125 nS
58.125 nS
45 nS
105 mA
115mA
8 mA
165 mA
200 mA
105 mA
6 mA
245 mA
DDR2-800
5-5-5/6-6-6
-25/25I/25J
2.5 nS
8 nS
2.5 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
12.5 nS
7.8 μS*
2, 3
7.8 μS*
1
3.9 μS*
4
3.9 μS*
4
12.5 nS
57.5 nS
45 nS
90 mA
100 mA
8 mA
140 mA
165 mA
95 mA
6 mA
200 mA
DDR2-800
5-5-5/6-6-6
25L
2.5 nS
8 nS
2.5 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
12.5 nS
*
2
7.8 μS*
1
3.9 μS*
4
*
2
12.5 nS
57.5 nS
45 nS
90 mA
100 mA
6 mA
140 mA
165 mA
95 mA
3 mA
200 mA
DDR2-667
5-5-5
-3
3 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
15 nS
*
2
7.8 μS*
1
3.9 μS*
4
*
2
15 nS
60 nS
45 nS
80 mA
90 mA
8 mA
125 mA
150 mA
90 mA
6 mA
180 mA
Average clock period
@CL = 5
@CL = 4
@CL = 3
t
RCD
Active to Read/Write Command Delay Time
-40°C ≤ T
CASE
≤ 85°C
Average periodic
refresh Interval
0°C ≤ T
CASE
≤ 85°C
85°C < T
CASE
≤ 95°C
95°C < T
CASE
≤ 105°C
t
REFI
t
RP
t
RC
t
RAS
I
DD0
I
DD1
I
DD2P
I
DD4R
I
DD4W
I
DD5B
I
DD6
I
DD7
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Operating current
Operation current (Single bank)
Precharge power-down current
Operating burst read current
Operating burst write current
Burst refresh current
Self refresh current (T
CASE
≤ 85C)
Operating bank interleave read current
Notes:
1. All speed grades support 0°C ≤ T
CASE
≤ 85°C with full JEDEC AC and DC specifications.
2. For -18, -25, 25L and -3 speed grades, -40°C ≤ T
CASE
< 0°C and 95°C < T
CASE
≤ 105°C operating temperature range are
not available.
3. 18I and 25I speed grades support -40°C ≤ T
CASE
≤ 85°C with full JEDEC AC and DC specifications.
4. For -18, 18I, -25, 25L, 25I and -3 speed grades, T
CASE
is able to extend to 95°C. For 18J and 25J speed grades, T
CASE
is
able to extend to 105°C. They are with doubling Auto Refresh commands in frequency to a 32 mS period ( t
REFI
= 3.9 µS)
and to enter to Self Refresh mode at this high temperature range via A7 “1” on EMR (2).
Publication Release Date: Jan. 23, 2017
Revision: A09
-5-
Embedded System
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