W6351G6KB
4M
8 BANKS
16 BIT DDR3 SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
8.1
8.2
GENERAL DESCRIPTION ................................................................................................................... 5
FEATURES ........................................................................................................................................... 5
ORDER INFORMATION ....................................................................................................................... 6
KEY PARAMETERS ............................................................................................................................. 6
BALL CONFIGURATION ...................................................................................................................... 7
BALL DESCRIPTION ............................................................................................................................ 8
BLOCK DIAGRAM .............................................................................................................................. 10
FUNCTIONAL DESCRIPTION ............................................................................................................ 11
Basic Functionality .............................................................................................................................. 11
RESET and Initialization Procedure .................................................................................................... 11
8.2.1
Power-up Initialization Sequence ..................................................................................... 11
8.2.2
Reset Initialization with Stable Power .............................................................................. 13
Programming the Mode Registers....................................................................................................... 14
8.3.1
Mode Register MR0 ......................................................................................................... 16
8.3.1.1
Burst Length, Type and Order ................................................................................ 17
8.3.1.2
CAS Latency........................................................................................................... 17
8.3.1.3
Test Mode............................................................................................................... 18
8.3.1.4
DLL Reset............................................................................................................... 18
8.3.1.5
Write Recovery ....................................................................................................... 18
8.3.1.6
Precharge PD DLL ................................................................................................. 18
8.3.2
Mode Register MR1 ......................................................................................................... 19
8.3.2.1
DLL Enable/Disable ................................................................................................ 19
8.3.2.2
Output Driver Impedance Control ........................................................................... 20
8.3.2.3
ODT RTT Values .................................................................................................... 20
8.3.2.4
Additive Latency (AL) ............................................................................................. 20
8.3.2.5
Write leveling .......................................................................................................... 20
8.3.2.6
Output Disable ........................................................................................................ 20
8.3.3
Mode Register MR2 ......................................................................................................... 21
8.3.3.1
Partial Array Self Refresh (PASR) .......................................................................... 22
8.3.3.2
CAS Write Latency (CWL) ...................................................................................... 22
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) ............................. 22
8.3.3.4
Dynamic ODT (Rtt_WR) ......................................................................................... 22
8.3.4
Mode Register MR3 ......................................................................................................... 23
8.3.4.1
Multi Purpose Register (MPR) ................................................................................ 23
No OPeration (NOP) Command .......................................................................................................... 24
Deselect Command............................................................................................................................. 24
DLL-off Mode ...................................................................................................................................... 24
DLL on/off switching procedure ........................................................................................................... 25
8.7.1
DLL
“on”
to DLL
“off”
Procedure .......................................................................... 25
8.7.2
8.8
DLL
“off”
to DLL
“on”
Procedure .......................................................................... 26
Input clock frequency change ............................................................................................................. 27
8.8.1
Frequency change during Self-Refresh............................................................................ 27
8.8.2
Frequency change during Precharge Power-down .......................................................... 27
Write Leveling ..................................................................................................................................... 29
8.3
8.4
8.5
8.6
8.7
8.9
Publication Release Date: Dec. 20, 2016
Revision: A01
-1-
W6351G6KB
8.9.1
DRAM setting for write leveling & DRAM termination function in that mode .................... 30
8.9.2
Write Leveling Procedure ................................................................................................. 30
8.9.3
Write Leveling Mode Exit ................................................................................................. 32
Multi Purpose Register ........................................................................................................................ 33
8.10.1
MPR Functional Description ............................................................................................. 34
8.10.2
MPR Register Address Definition ..................................................................................... 35
8.10.3
Relevant Timing Parameters ............................................................................................ 35
8.10.4
Protocol Example ............................................................................................................. 35
ACTIVE Command.............................................................................................................................. 41
PRECHARGE Command .................................................................................................................... 41
READ Operation ................................................................................................................................. 42
8.13.1
READ Burst Operation ..................................................................................................... 42
8.13.2
READ Timing Definitions .................................................................................................. 43
8.13.2.1
READ Timing; Clock to Data Strobe relationship.................................................... 44
8.13.2.2
READ Timing; Data Strobe to Data relationship ..................................................... 45
8.13.2.3
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ............................................. 46
8.13.2.4
tRPRE Calculation .................................................................................................. 47
8.13.2.5
tRPST Calculation .................................................................................................. 47
8.13.2.6
Burst Read Operation followed by a Precharge...................................................... 53
WRITE Operation ................................................................................................................................ 55
8.14.1
DDR3 Burst Operation ..................................................................................................... 55
8.14.2
WRITE Timing Violations ................................................................................................. 55
8.14.2.1
Motivation ............................................................................................................... 55
8.14.2.2
Data Setup and Hold Violations .............................................................................. 55
8.14.2.3
Strobe to Strobe and Strobe to Clock Violations..................................................... 55
8.14.2.4
Write Timing Parameters ........................................................................................ 55
8.14.3
Write Data Mask............................................................................................................... 56
8.14.4
tWPRE Calculation........................................................................................................... 57
8.14.5
tWPST Calculation ........................................................................................................... 57
Refresh Command .............................................................................................................................. 64
Self-Refresh Operation ....................................................................................................................... 66
Power-Down Modes ............................................................................................................................ 68
8.17.1
Power-Down Entry and Exit ............................................................................................. 68
8.17.2
Power-Down clarifications - Case 1 ................................................................................. 74
8.17.3
Power-Down clarifications - Case 2 ................................................................................. 74
8.17.4
Power-Down clarifications - Case 3 ................................................................................. 75
ZQ Calibration Commands .................................................................................................................. 76
8.18.1
ZQ Calibration Description ............................................................................................... 76
8.18.2
ZQ Calibration Timing ...................................................................................................... 77
8.18.3
ZQ External Resistor Value, Tolerance, and Capacitive loading ...................................... 77
On-Die Termination (ODT) .................................................................................................................. 78
8.19.1
ODT Mode Register and ODT Truth Table ...................................................................... 78
8.19.2
Synchronous ODT Mode .................................................................................................. 79
8.19.2.1
ODT Latency and Posted ODT ............................................................................... 79
8.19.2.2
Timing Parameters ................................................................................................. 79
8.19.2.3
ODT during Reads .................................................................................................. 81
8.19.3
Dynamic ODT .................................................................................................................. 82
8.19.3.1
Functional Description: ........................................................................................... 82
8.19.3.2
ODT Timing Diagrams ............................................................................................ 83
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
Publication Release Date: Dec. 20, 2016
Revision: A01
-2-
W6351G6KB
8.19.4
Asynchronous ODT Mode ................................................................................................ 87
8.19.4.1
Synchronous to Asynchronous ODT Mode Transitions .......................................... 88
8.19.4.2
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry .. 88
8.19.4.3
Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit..... 91
8.19.4.4
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE
low periods
92
9.
9.1
9.2
9.3
10.
OPERATION MODE ........................................................................................................................... 93
Command Truth Table ........................................................................................................................ 93
CKE Truth Table ................................................................................................................................. 95
Simplified State Diagram ..................................................................................................................... 96
ELECTRICAL CHARACTERISTICS ................................................................................................... 97
10.1 Absolute Maximum Ratings ................................................................................................................ 97
10.2 Operating Temperature Condition ....................................................................................................... 97
10.3 DC & AC Operating Conditions ........................................................................................................... 97
10.3.1
Recommended DC Operating Conditions ........................................................................ 97
10.4 Input and Output Leakage Currents .................................................................................................... 98
10.5 Interface Test Conditions .................................................................................................................... 98
10.6 DC and AC Input Measurement Levels ............................................................................................... 99
10.6.1
DC and AC Input Levels for Single-Ended Command and Address Signals .................... 99
10.6.2
DC and AC Input Levels for Single-Ended Data Signals .................................................. 99
10.6.3
Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) ........... 101
10.6.4
Single-ended requirements for differential signals ......................................................... 102
10.6.5
Differential Input Cross Point Voltage ............................................................................ 103
10.6.6
Slew Rate Definitions for Single-Ended Input Signals .................................................... 104
10.6.7
Slew Rate Definitions for Differential Input Signals ........................................................ 104
10.7 DC and AC Output Measurement Levels .......................................................................................... 105
10.7.1
Output Slew Rate Definition and Requirements ............................................................. 105
10.7.1.1
Single Ended Output Slew Rate ........................................................................... 106
10.7.1.2
Differential Output Slew Rate ............................................................................... 107
10.8 Output Driver DC Electrical Characteristics ...................................................................................... 108
10.8.1
Output Driver Temperature and Voltage sensitivity ........................................................ 110
10.9 On-Die Termination (ODT) Levels and Characteristics ..................................................................... 111
10.9.1
ODT Levels and I-V Characteristics ............................................................................... 111
10.9.2
ODT DC Electrical Characteristics ................................................................................. 112
10.9.3
ODT Temperature and Voltage sensitivity ..................................................................... 112
10.9.4
Design guide lines for RTT
PU
and RTT
PD
....................................................................... 113
10.10
ODT Timing Definitions............................................................................................................ 114
10.10.1
Test Load for ODT Timings ............................................................................................ 114
10.10.2
ODT Timing Definitions .................................................................................................. 114
10.11
Input/Output Capacitance ........................................................................................................ 118
10.12
Overshoot and Undershoot Specifications............................................................................... 119
10.12.1
AC Overshoot /Undershoot Specification for Address and Control Pins: ....................... 119
10.12.2
AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins: ......... 119
10.13
IDD and IDDQ Specification Parameters and Test Conditions ................................................ 120
10.13.1
IDD and IDDQ Measurement Conditions ....................................................................... 120
10.13.2
IDD Current Specifications ............................................................................................. 130
10.14
Clock Specification .................................................................................................................. 131
10.15
Speed Bins .............................................................................................................................. 132
10.15.1
DDR3-1333 Speed Bin and Operating Conditions ......................................................... 132
10.15.2
DDR3-1600 Speed Bin and Operating Conditions ......................................................... 133
Publication Release Date: Dec. 20, 2016
Revision: A01
-3-
W6351G6KB
10.16
AC Characteristics ................................................................................................................... 134
10.16.1
AC Timing and Operating Condition for -12/-15 speed grades ...................................... 134
10.16.2
Timing Parameter Notes ................................................................................................ 138
10.16.3
Address / Command Setup, Hold and Derating ............................................................. 141
10.16.4
Data Setup, Hold and Slew Rate Derating ..................................................................... 147
PACKAGE SPECIFICATION ............................................................................................................ 149
REVISION HISTORY ........................................................................................................................ 150
11.
12.
Publication Release Date: Dec. 20, 2016
Revision: A01
-4-
W6351G6KB
1. GENERAL DESCRIPTION
The W6351G6KB is a 512M bits DDR3 SDRAM, organized as 4,194,304 words
8 banks
16 bits.
This device achieves high speed transfer rates up to 1600 Mb/sec/pin (DDR3-1600) for general
applications. W6351G6KB is sorted into two speed grades: -12 and -15. The -12 is compliant to the
DDR3-1600 (11-11-11) specification. The -15 is compliant to the DDR3-1333 (9-9-9) specification.
The W6351G6KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: V
DD
, V
DDQ
= 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 8, 9, 10 and 11
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Data masks (DM) for write data
Programmable CAS Write Latency (CWL) per operating frequency
Write Latency WL = AL + CWL
Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence
System level timing calibration support via write leveling and MPR read pattern
ZQ Calibration for output driver and ODT using external reference resistor to ground
Asynchronous RESET# pin for Power-up initialization sequence and reset function
Programmable on-die termination (ODT) for data, data mask and differential strobe pairs
Dynamic ODT mode for improved signal integrity and preselectable termination impedances during
writes
2K Byte page size
Interface: SSTL_15
Packaged in TFBGA 96 Ball (9x13 mm
2
), using lead free materials with RoHS compliant
Publication Release Date: Dec. 20, 2016
Revision: A01
-5-
Microcontroller MCU
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