512Mb: x16, x32 Automotive LPDDR SDRAM
Features
Automotive LPDDR SDRAM
MT46H32M16LF – 8 Meg x 16 x 4 banks
MT46H16M32LF – 4 Meg x 32 x 4 banks
MT46H16M32LG – 4 Meg x 32 x 4 banks
Features
• V
DD
/V
DDQ
= 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data; one mask
per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh, 32ms for automotive temperature
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
-5
-6
Clock Rate
200 MHz
166 MHz
Access Time
5.0ns
5.0ns
Options
• V
DD
/V
DDQ
– 1.8V/1.8V
• Configuration
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
– 16 Meg x 32 (4 Meg x 32 x 4 banks)
• Addressing
– JEDEC-standard addressing
• Plastic "green" package
– 60-ball VFBGA (8mm x 9mm)
1
– 90-ball VFBGA (8mm x 13mm)
2
– 90-ball VFBGA (8mm x 13mm)
2
• Timing – cycle time
– 5ns @ CL = 3 (200 MHz)
– 6ns @ CL = 3 (166 MHz)
• Power
– Standard I
DD2
/I
DD6
– Low-power I
DD2
/I
DD6
• Product certification
– Automotive
• Operating temperature range
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
• Design revision
Notes:
Marking
H
32M16
16M32
LF
BF
B5
BQ
-5
-6
None
L
A
IT
AT
:C
1. Only available for x16 configuration.
2. Only available for x32 configuration.
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t67m_embedded_lpddr_512mb.pdf - Rev. E 05/18 EN
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Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
512Mb: x16, x32 Automotive LPDDR SDRAM
Features
Table 2: Configuration Addressing
Architecture
Configuration
Refresh count
Row addressing
Column addressing
32 Meg x 16
8 Meg x 16 x 4 banks
8K
8K A[12:0]
1K A[9:0]
16 Meg x 32
4 Meg x 32 x 4 banks
8K
8K A[12:0]
512 A[8:0]
Figure 1: 512Mb Mobile LPDDR Part Numbering
MT 46
Micron Technology
Product Family
46 = Mobile LPDDR
H
32M16 LF BF
-6
A
AIT :C
Design Revision
:C = Third generation
Operating Temperature
IT = Industrial
AT = Automotive
Operating Voltage
H = 1.8/1.8V
Product Certification
A = Automotive
Configuration
32 Meg x 16
16 Meg x 32
Power
Blank = Standard I
DD2
/I
DD6
L = Low-power I
DD2
/I
DD6
Addressing
LF = JEDEC-standard
Cycle Time (CL = 3)
-5 = 5ns
t
CK
-6 = 6ns
t
CK
Package Codes
BF = 60-ball (8mm x 9mm) VFBGA, “green”
B5 = 90-ball (8mm x 13mm) VFBGA, “green”
BQ = 90-ball (8mm x 13mm) VFBGA, “green”
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
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t67m_embedded_lpddr_512mb.pdf - Rev. E 05/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
512Mb: x16, x32 Automotive LPDDR SDRAM
Features
Contents
Important Notes and Warnings ......................................................................................................................... 8
General Description ......................................................................................................................................... 8
Functional Block Diagrams ............................................................................................................................. 10
Ball Assignments ............................................................................................................................................ 12
Ball Descriptions ............................................................................................................................................ 14
Package Dimensions ....................................................................................................................................... 16
Electrical Specifications .................................................................................................................................. 18
Electrical Specifications – I
DD
Parameters ........................................................................................................ 22
Electrical Specifications – AC Operating Conditions ......................................................................................... 28
Output Drive Characteristics ........................................................................................................................... 33
Functional Description ................................................................................................................................... 36
Commands .................................................................................................................................................... 37
DESELECT ................................................................................................................................................. 38
NO OPERATION ......................................................................................................................................... 38
LOAD MODE REGISTER ............................................................................................................................. 38
ACTIVE ...................................................................................................................................................... 38
READ ......................................................................................................................................................... 39
WRITE ....................................................................................................................................................... 40
PRECHARGE .............................................................................................................................................. 41
BURST TERMINATE ................................................................................................................................... 42
AUTO REFRESH ......................................................................................................................................... 42
SELF REFRESH ........................................................................................................................................... 43
DEEP POWER-DOWN ................................................................................................................................. 43
Truth Tables ................................................................................................................................................... 44
State Diagram ................................................................................................................................................ 49
Initialization .................................................................................................................................................. 50
Standard Mode Register .................................................................................................................................. 53
Burst Length .............................................................................................................................................. 54
Burst Type .................................................................................................................................................. 54
CAS Latency ............................................................................................................................................... 55
Operating Mode ......................................................................................................................................... 56
Extended Mode Register ................................................................................................................................. 57
Temperature-Compensated Self Refresh ...................................................................................................... 57
Partial-Array Self Refresh ............................................................................................................................ 58
Output Drive Strength ................................................................................................................................ 58
Status Read Register ....................................................................................................................................... 59
Bank/Row Activation ...................................................................................................................................... 61
READ Operation ............................................................................................................................................. 62
WRITE Operation ........................................................................................................................................... 73
PRECHARGE Operation .................................................................................................................................. 85
Auto Precharge ............................................................................................................................................... 85
Concurrent Auto Precharge ......................................................................................................................... 85
AUTO REFRESH Operation ............................................................................................................................. 91
SELF REFRESH Operation ............................................................................................................................... 92
Power-Down .................................................................................................................................................. 94
Deep Power-Down ..................................................................................................................................... 95
Clock Change Frequency ................................................................................................................................ 97
Revision History ............................................................................................................................................. 98
Rev. E – 05/18 ............................................................................................................................................. 98
Rev. D – 02/14 ............................................................................................................................................. 98
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t67m_embedded_lpddr_512mb.pdf - Rev. E 05/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
512Mb: x16, x32 Automotive LPDDR SDRAM
Features
Rev. C – 11/13 ............................................................................................................................................. 98
Rev. B – 03/13 ............................................................................................................................................. 98
Rev. A – 12/12 ............................................................................................................................................. 98
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t67m_embedded_lpddr_512mb.pdf - Rev. E 05/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
512Mb: x16, x32 Automotive LPDDR SDRAM
Features
List of Figures
Figure 1: 512Mb Mobile LPDDR Part Numbering .............................................................................................. 2
Figure 2: Functional Block Diagram (x16) ....................................................................................................... 10
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 11
Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 12
Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 13
Figure 6: 60-Ball VFBGA (8mm x 9mm); Package Code: BF .............................................................................. 16
Figure 7: 90-Ball VFBGA (8mm x 13mm); Package Codes: B5 (SAC105), BQ (SAC305) ........................................ 17
Figure 8: SSTL Clock Input ............................................................................................................................. 20
Figure 9: Differential Clock Amplitude ........................................................................................................... 20
Figure 10: Typical Self Refresh Current vs. Temperature .................................................................................. 27
Figure 11: ACTIVE Command ........................................................................................................................ 39
Figure 12: READ Command ........................................................................................................................... 40
Figure 13: WRITE Command ......................................................................................................................... 41
Figure 14: PRECHARGE Command ................................................................................................................ 42
Figure 15: DEEP POWER-DOWN Command ................................................................................................... 43
Figure 16: Simplified State Diagram ............................................................................................................... 49
Figure 17: Initialize and Load Mode Registers ................................................................................................. 51
Figure 18: Alternate Initialization with CKE LOW ............................................................................................ 52
Figure 19: Standard Mode Register Definition ................................................................................................. 53
Figure 20: CAS Latency .................................................................................................................................. 56
Figure 21: Extended Mode Register ................................................................................................................ 57
Figure 22: Status Read Register Timing ........................................................................................................... 59
Figure 23: Status Register Definition .............................................................................................................. 60
Figure 24: READ Burst ................................................................................................................................... 63
Figure 25: Consecutive READ Bursts .............................................................................................................. 64
Figure 26: Nonconsecutive READ Bursts ........................................................................................................ 65
Figure 27: Random Read Accesses .................................................................................................................. 66
Figure 28: Terminating a READ Burst ............................................................................................................. 67
Figure 29: READ-to-WRITE ............................................................................................................................ 68
Figure 30: READ-to-PRECHARGE .................................................................................................................. 69
Figure 31: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x16) .................................................... 70
Figure 32: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x32) .................................................... 71
Figure 33: Data Output Timing –
t
AC and
t
DQSCK .......................................................................................... 72
Figure 34: Data Input Timing ......................................................................................................................... 74
Figure 35: Write – DM Operation .................................................................................................................... 75
Figure 36: WRITE Burst ................................................................................................................................. 76
Figure 37: Consecutive WRITE-to-WRITE ....................................................................................................... 77
Figure 38: Nonconsecutive WRITE-to-WRITE ................................................................................................. 77
Figure 39: Random WRITE Cycles .................................................................................................................. 78
Figure 40: WRITE-to-READ – Uninterrupting ................................................................................................. 79
Figure 41: WRITE-to-READ – Interrupting ...................................................................................................... 80
Figure 42: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 81
Figure 43: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 82
Figure 44: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 83
Figure 45: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 84
Figure 46: Bank Read – With Auto Precharge ................................................................................................... 87
Figure 47: Bank Read – Without Auto Precharge .............................................................................................. 88
Figure 48: Bank Write – With Auto Precharge .................................................................................................. 89
Figure 49: Bank Write – Without Auto Precharge ............................................................................................. 90
Figure 50: Auto Refresh Mode ........................................................................................................................ 91
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t67m_embedded_lpddr_512mb.pdf - Rev. E 05/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
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