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MT55L128L36F1T-12IT

Description
ZBT SRAM, 128KX36, 9ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
Categorystorage   
File Size491KB,31 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

MT55L128L36F1T-12IT Overview

ZBT SRAM, 128KX36, 9ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

MT55L128L36F1T-12IT Parametric

Parameter NameAttribute value
MakerCypress Semiconductor
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Is SamacsysN
Maximum access time9 ns
JESD-30 codeR-PQFP-G100
length20 mm
memory density4718592 bit
Memory IC TypeZBT SRAM
memory width36
Number of functions1
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX36
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
width14 mm
Base Number Matches1
PRELIMINARY
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
4Mb
ZBT
®
SRAM
FEATURES
High frequency and 100 percent bus utilization
Fast cycle times: 10ns, 11ns, and 12ns
Single +3.3V ±5% power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
Advanced control logic for minimum control
signal interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to
eliminate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or interleaved burst modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 8Mb, and
16Mb ZBT SRAM family
165-pin FBGA package
100-pin TSOP package
119-pin BGA package
Automatic power-down
MT55L256L18F1, MT55L128L32F1,
MT55L128L36F1; MT55L256V18F1,
MT55L128V32F1, MT55L128V36F1
3.3V V
DD
, 3.3V or 2.5V I/O
100-Pin TQFP
1
165-Pin FBGA
(Preliminary Package Data)
OPTIONS
• Timing (Access/Cycle/MHz)
7.5ns/10ns/100 MHz
8.5ns/11ns/90 MHz
9ns/12ns/83 MHz
• Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
• Package
100-pin TQFP
165-pin FBGA
119-pin, 14mm x 22mm BGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
Part Number Example:
MARKING*
-10
-11
-12
MT55L256L18F1
MT55L128L32F1
MT55L128L36F1
MT55L256V18F1
MT55L128V32F1
MT55L128V36F1
T
F
B
None
IT
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA (PBGA).
119-Pin BGA
2
MT55L256L18F1T-12
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_C.p65 – Rev. 6/01
* A Part Marking Guide for the FBGA devices can be found on Micron’s
web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
confgurations. Contact factory for more information.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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