If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, V
DD
Voltage at any pin
ESD Susceptibility (Note 4)
Soldering Information
N Package (10s)
M Package
Vapor Phase (60s)
Infrared (15s)
15V
(GND −0.2V) to (V
DD
+0.2V)
3000V
260˚C
215˚C
220˚C
Operating Ratings
(Notes 1, 2)
Temperature Range
T
MIN
≤
T
A
≤
T
MAX
Thermal Resistance
M08A Package,
θ
JA
N08E Package,
θ
JA
Supply Voltage
167˚C/W
102˚C/W
4.5V to 12V
−40˚C
≤
T
A
≤
+85˚C
Electrical Characteristics
(Notes 1, 2)
The following specifications apply for V
DD
= +12V (V
REF
IN = +6V), V
IN
= 5.5 V
pk
, and f = 1 kHz, unless otherwse specified.
Limits apply for T
A
= 25˚C. Digital inputs are TTL and CMOS compatible.
LM1971
Symbol
I
S
THD
e
IN
Parameter
Supply Current
Total Harmonic Distortion
Noise
Conditions
Digital Inputs Tied to 6V
V
IN
= 0.5V
pk
@
0 dB Attenuation
Input is AC Grounded
@
−12 dB Attenuation
A-Weighted (Note 7)
Referenced to Full Scale = +6 V
pk
0 dB to −62 dB
Attenuation
Attenuation
Attenuation
Attenuation
Attenuation
@
0 dB
@
−20 dB
@
−40 dB
@
−60 dB
@
−62 dB
Typical
(Note 5)
1.8
0.0008
4.0
Limit
(Note 6)
3
0.003
Units
(Limits)
mA (max)
% (max)
µV
DR
A
M
Dynamic Range
Mute Attenuation
Attenuation Step Size Error
Absolute Attenuation
115
102
0.009
0.1
−20.3
−40.5
−60.6
−62.6
5.8
96
0.2
0.5
−19.0
−38.0
−57.0
−59.0
100
20
60
100
2
2.0
0.8
dB
dB (min)
dB (max)
dB
dB
dB
dB
dB
(min)
(min)
(min)
(min)
(min)
dB
kΩ (min)
kΩ (max)
nA (max)
MHz (max)
V (min)
V (max)
I
LEAK
R
IN
I
IN
f
CLK
V
IH
V
IL
Analog Input Leakage Current
Frequency Response
AC Input Impedance
Input Current
Clock Frequency
High-Level Input Voltage
Low-Level Input Voltage
Input is AC Grounded
20 Hz–100 kHz
Pin 8, V
IN
= 1.0 V
pk
, f = 1 kHz
@
Pins 4, 5, 6
@
0V
@
Pins 4, 5, 6
@
Pins 4, 5, 6
nA (max)
±
0.1
40
1.0
3
<
V
IN
<
5V
Note 1:
Absolute Maximum Ratings
indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Electrical Characteristics
state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 2:
All voltages are measured with respect to the GND pin (pin 3), unless otherwise specified.
Note 3:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
,
θ
JA
, and the ambient temperature T
A
. The maximum
allowable power dissipation is P
D
= (T
JMAX
– T
A
)/θ
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For the LM1971N and LM1971M,
T
JMAX
= +150˚C, and the typical junction-to-ambient thermal resistance,
θ
JA
, when board mounted is 102˚ C/W and 167˚ C/W, respectively.
Note 4:
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5:
Typicals are measured at 25˚C and represent the parametric norm.
Note 6:
Limits are guarantees that all parts are tested in production to meet the stated values.
Note 7:
Due to production test limitations, there is no limit for the Noise test. Please refer to the noise measurements in the Typical Performance Characteristics
section.
3
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LM1971
Pin Descriptions
V
REF
IN (1):
The V
REF
IN pin provides the reference for the
analog input signal. This pin should be biased at half of the
supply voltage, V
DD
, as shown in
Figure 1
and
Figure 6.
OUT (2):
The attenuated analog output signal comes from
this pin.
GND (3):
The GND pin references the digital input signals
and is the lower voltage reference for the IC. Typically this
pin would be labeled “V
SS
” but the ground reference for the
digital logic input control is tied to this same point. With a
higher pin-count there would generally be separate pins for
these functions; V
SS
and Logic Ground. It is intended that
the LM1971 always be operated using a single voltage sup-
ply configuration, for which pin 3 (GND) should always be at
system ground. If a bipolar or split-supply configuration are
desired, level shifting circuitry is needed for the digital logic
control pins as they would be referenced through pin 3 which
would be at the negative supply. It is highly recommended,
however, that the LM1971 be used in a unipolar or
single-supply configuration.
LOAD (4):
The LOAD input accepts a TTL or CMOS level
signal. This is the enable pin of the device, allowing data to
be clocked in while this input is low (0V). The GND pin is the
reference for this signal.
DATA (5):
The DATA input accepts a TTL or CMOS level
signal. This pin is used to accept serial data from a micro-
controller that will be latched and decoded to change the
channel’s attenuation level. The GND pin is the reference for
this signal.
CLOCK (6):
The CLOCK input accepts a TTL or CMOS level
signal. The clock input is used to load data into the internal
shift register on the rising edge of the input clock waveform.
The GND pin is the reference for this signal.
V
DD
(7):
The positive voltage supply should be placed to this
pin.
IN (8):
The analog input signal should be placed to this pin.
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