AD9864BCPZRL datasheet, PDF - EEWORLD Datasheet

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AD9864BCPZRL: Descriptionbraid; CategoryWireless rf/communication Telecom circuit; File Size1MB，47 Pages; ManufacturerADI; Websitehttps://www.analog.com; Environmental Compliance

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AD9864BCPZRL Parametric

Parameter Name	Attribute value
Brand Name	Analog Devices Inc
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Maker	ADI
Parts packaging code	QFN
package instruction	HVQCCN, LCC48,.27SQ,20
Contacts	48
Manufacturer packaging code	CP-48-1
Reach Compliance Code	compliant
ECCN code	5A991.B.7
Samacsys Description	RF Receiver IF Digitizing Subsystem
data rate	20 Mbps
JESD-30 code	S-XQCC-N48
JESD-609 code	e3
length	7 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC48,.27SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Maximum seat height	1 mm
Nominal supply voltage	3 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	7 mm
Base Number Matches	1

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Data Sheet

FEATURES

10 MHz to 300 MHz input frequency

6.8 kHz to 270 kHz output signal bandwidth

7.5 dB single sideband noise figure (SSB NF)

−7.0 dBm input third-order intercept (IIP3)

AGC free range up to −34 dBm

12 dB continuous AGC range

16 dB front-end attenuator

Baseband I/Q 16-bit (or 24-bit) serial digital output

LO and sampling clock synthesizers

Programmable decimation factor, output format, AGC, and

synthesizer settings

370 Ω input impedance

2.7 V to 3.6 V supply voltage

Low current consumption: 17 mA

48-lead LFCSP package

IF Digitizing Subsystem

AD9864

GENERAL DESCRIPTION

The

AD9864

is a general-purpose IF subsystem that digitizes a

low level, 10 MHz to 300 MHz IF input with a signal bandwidth

ranging from 6.8 kHz to 270 kHz. The signal chain of the

AD9864

consists of a low noise amplifier (LNA), a mixer, a band-pass Σ-∆

analog-to-digital converter (ADC), and a decimation filter with

programmable decimation factor. An automatic gain control

(AGC) circuit gives the

AD9864

12 dB of continuous gain

adjustment. Auxiliary blocks include both clock and local

oscillator (LO) synthesizers.

The high dynamic range of the

AD9864

and inherent antialiasing

provided by the band-pass Σ-∆ converter allow the device to cope

with blocking signals up to 95 dB stronger than the desired signal.

This attribute often reduces the cost of a radio by reducing IF

filtering requirements. Also, it enables multimode radios of varying

channel bandwidths, allowing the IF filter to be specified for the

largest channel bandwidth.

The SPI port programs numerous parameters of the

AD9864,

allowing the device to be optimized for any given application.

Programmable parameters include synthesizer divide ratios, AGC

attenuation and attack/decay time, received signal strength level,

decimation factor, output data format, 16 dB attenuator, and the

selected bias currents.

The

AD9864

is available in a 48-lead LFCSP package and operates

from a single 2.7 V to 3.6 V supply. The total power consumption

is typically 56 mW and a power-down mode is provided via

serial interfacing.

APPLICATIONS

Multimode narrow-band radio products

Analog/digital UHF/VHF FDMA receivers

TETRA, APCO25, GSM/EDGE

Portable and mobile radio products

SATCOM terminals

FUNCTIONAL BLOCK DIAGRAM

MXOP MXON IF2P IF2N

GCP GCN

DAC

–16dB

DECIMATION

FILTER

AGC

AD9864

IFIN

LNA

Σ-Δ ADC

FORMATTING/SSI

DOUTA

DOUTB

CLKOUT

FREF

CONTROL LOGIC

SYN

VOLTAGE

REFERENCE

CLK SYN

SPI

IOUTL

LOP LON

LO VCO AND

LOOP FILTER

IOUTC

CLKP

CLKN

VREFP VCM VREFN

SYNCB

04319-0-001

LOOP FILTER

Figure 1.

Protected by U.S. Patent No. 5,969,657; other patents pending.

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

AD9864

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Digital Specifications ................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Functional Descriptions .......................... 7

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 14

Serial Peripheral Interface (SPI) ................................................... 15

Theory of Operation ...................................................................... 17

Introduction ................................................................................ 17

Serial Port Interface (SPI) .......................................................... 18

Power-On Reset .......................................................................... 19

Synchronous Serial Interface (SSI) ........................................... 19

Data Sheet

SSI Control Registers ................................................................. 21

Synchronization Using SYNCB ................................................ 24

Interfacing to DSPs .................................................................... 24

Power Control ............................................................................. 24

LO Synthesizer ............................................................................ 25

Clock Synthesizer ....................................................................... 26

IF LNA/Mixer ............................................................................. 28

Band-Pass Σ-Δ ADC .................................................................. 29

Decimation Filter ....................................................................... 32

Variable Gain Amplifier Operation with Automatic

Gain Control ............................................................................... 33

Applications Considerations ..................................................... 38

External Passive Component Requirements .......................... 40

Applications ................................................................................ 40

Layout Example, Evaluation Board, and Software ................. 45

SPI Initialization Example ......................................................... 45

Device SPI Initialization ............................................................ 46

Outline Dimensions ....................................................................... 47

Ordering Guide .......................................................................... 47

REVISION HISTORY

2/16—Rev. 0 to Rev. A

Changes to Figure 2 .......................................................................... 7

Changes to Typical Performance Characteristics Section ........... 9

Changes to Figure 19 ...................................................................... 11

Changes to Table 6 .......................................................................... 16

Changed General Description Section to Introduction Section ... 17

Changes to Serial Port Interface (SPI) Section ........................... 18

Added Figure 31; Renumbered Sequentially .............................. 19

Added Power-On Reset Section ................................................... 19

Deleted Table 9; Renumbered Sequentially ................................ 19

Added SSI Control Registers Section and Table 8 to Table 13 .... 21

Changes to Synchronization Using SYNCB Section and

Figure 38 .......................................................................................... 24

Changes to Clock Synthesizer Section ......................................... 26

Changes to Band-Pass Σ-Δ ADC Section and Table 20 ............ 30

Changes to Table 21 ....................................................................... 31

Changes to Variable Gain Control Section ................................. 34

Deleted Table 17 ............................................................................. 34

Added Figure 64 ............................................................................. 36

Changes to Figure 72...................................................................... 40

Changes to Layout Example, Evaluation Board, and

Software Section ............................................................................. 45

Added Figure 77 and SPI Initialization Example Section ......... 45

Added Device SPI Initialization Section and Table 24 .............. 46

Updated Outline Dimensions ....................................................... 47

Changes to Ordering Guide .......................................................... 47

8/03—Revision 0: Initial Version

Rev. A | Page 2 of 47

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