Data Sheet
FEATURES
10 MHz to 300 MHz input frequency
6.8 kHz to 270 kHz output signal bandwidth
7.5 dB single sideband noise figure (SSB NF)
−7.0 dBm input third-order intercept (IIP3)
AGC free range up to −34 dBm
12 dB continuous AGC range
16 dB front-end attenuator
Baseband I/Q 16-bit (or 24-bit) serial digital output
LO and sampling clock synthesizers
Programmable decimation factor, output format, AGC, and
synthesizer settings
370 Ω input impedance
2.7 V to 3.6 V supply voltage
Low current consumption: 17 mA
48-lead LFCSP package
IF Digitizing Subsystem
AD9864
GENERAL DESCRIPTION
The
AD9864
1
is a general-purpose IF subsystem that digitizes a
low level, 10 MHz to 300 MHz IF input with a signal bandwidth
ranging from 6.8 kHz to 270 kHz. The signal chain of the
AD9864
consists of a low noise amplifier (LNA), a mixer, a band-pass Σ-∆
analog-to-digital converter (ADC), and a decimation filter with
programmable decimation factor. An automatic gain control
(AGC) circuit gives the
AD9864
12 dB of continuous gain
adjustment. Auxiliary blocks include both clock and local
oscillator (LO) synthesizers.
The high dynamic range of the
AD9864
and inherent antialiasing
provided by the band-pass Σ-∆ converter allow the device to cope
with blocking signals up to 95 dB stronger than the desired signal.
This attribute often reduces the cost of a radio by reducing IF
filtering requirements. Also, it enables multimode radios of varying
channel bandwidths, allowing the IF filter to be specified for the
largest channel bandwidth.
The SPI port programs numerous parameters of the
AD9864,
allowing the device to be optimized for any given application.
Programmable parameters include synthesizer divide ratios, AGC
attenuation and attack/decay time, received signal strength level,
decimation factor, output data format, 16 dB attenuator, and the
selected bias currents.
The
AD9864
is available in a 48-lead LFCSP package and operates
from a single 2.7 V to 3.6 V supply. The total power consumption
is typically 56 mW and a power-down mode is provided via
serial interfacing.
APPLICATIONS
Multimode narrow-band radio products
Analog/digital UHF/VHF FDMA receivers
TETRA, APCO25, GSM/EDGE
Portable and mobile radio products
SATCOM terminals
FUNCTIONAL BLOCK DIAGRAM
MXOP MXON IF2P IF2N
GCP GCN
DAC
–16dB
DECIMATION
FILTER
AGC
AD9864
IFIN
LNA
Σ-Δ ADC
FORMATTING/SSI
DOUTA
DOUTB
FS
CLKOUT
FREF
CONTROL LOGIC
LO
SYN
VOLTAGE
REFERENCE
CLK SYN
SPI
IOUTL
LOP LON
LO VCO AND
LOOP FILTER
IOUTC
CLKP
CLKN
VREFP VCM VREFN
PC
PD
PE
SYNCB
04319-0-001
LOOP FILTER
Figure 1.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.
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Rev. A
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Trademarks and registered trademarks are the property of their respective owners.
AD9864
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Specifications ................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Functional Descriptions .......................... 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 14
Serial Peripheral Interface (SPI) ................................................... 15
Theory of Operation ...................................................................... 17
Introduction ................................................................................ 17
Serial Port Interface (SPI) .......................................................... 18
Power-On Reset .......................................................................... 19
Synchronous Serial Interface (SSI) ........................................... 19
Data Sheet
SSI Control Registers ................................................................. 21
Synchronization Using SYNCB ................................................ 24
Interfacing to DSPs .................................................................... 24
Power Control ............................................................................. 24
LO Synthesizer ............................................................................ 25
Clock Synthesizer ....................................................................... 26
IF LNA/Mixer ............................................................................. 28
Band-Pass Σ-Δ ADC .................................................................. 29
Decimation Filter ....................................................................... 32
Variable Gain Amplifier Operation with Automatic
Gain Control ............................................................................... 33
Applications Considerations ..................................................... 38
External Passive Component Requirements .......................... 40
Applications ................................................................................ 40
Layout Example, Evaluation Board, and Software ................. 45
SPI Initialization Example ......................................................... 45
Device SPI Initialization ............................................................ 46
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 47
REVISION HISTORY
2/16—Rev. 0 to Rev. A
Changes to Figure 2 .......................................................................... 7
Changes to Typical Performance Characteristics Section ........... 9
Changes to Figure 19 ...................................................................... 11
Changes to Table 6 .......................................................................... 16
Changed General Description Section to Introduction Section ... 17
Changes to Serial Port Interface (SPI) Section ........................... 18
Added Figure 31; Renumbered Sequentially .............................. 19
Added Power-On Reset Section ................................................... 19
Deleted Table 9; Renumbered Sequentially ................................ 19
Added SSI Control Registers Section and Table 8 to Table 13 .... 21
Changes to Synchronization Using SYNCB Section and
Figure 38 .......................................................................................... 24
Changes to Clock Synthesizer Section ......................................... 26
Changes to Band-Pass Σ-Δ ADC Section and Table 20 ............ 30
Changes to Table 21 ....................................................................... 31
Changes to Variable Gain Control Section ................................. 34
Deleted Table 17 ............................................................................. 34
Added Figure 64 ............................................................................. 36
Changes to Figure 72...................................................................... 40
Changes to Layout Example, Evaluation Board, and
Software Section ............................................................................. 45
Added Figure 77 and SPI Initialization Example Section ......... 45
Added Device SPI Initialization Section and Table 24 .............. 46
Updated Outline Dimensions ....................................................... 47
Changes to Ordering Guide .......................................................... 47
8/03—Revision 0: Initial Version
Rev. A | Page 2 of 47
Data Sheet
SPECIFICATIONS
AD9864
VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, f
CLK
= 18 MSPS, f
IF
= 109.65 MHz,
f
LO
= 107.4 MHz, f
REF
= 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation setting, synthesizers
in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Table 1.
Parameter
SYSTEM DYNAMIC PERFORMANCE
1
SSB Noise Figure at Minimum VGA Attenuation
2, 3
SSB Noise Figure at Maximum VGA Attenuation
2, 3
Dynamic Range with AGC Enabled
2, 3
IF Input Clip Point at Maximum VGA Attenuation
3
IF Input Clip Point at Minimum VGA Attenuation
3
Input Third-Order Intercept (IIP3)
Gain Variation over Temperature
LNA + MIXER
Maximum RF and LO Frequency Range
LNA Input Impedance
Mixer LO Input Resistance
LO SYNTHESIZER
LO Input Frequency
LO Input Amplitude
FREF Frequency (for Sinusoidal Input Only)
FREF Input Amplitude
FREF Slew Rate
Minimum Charge Pump Current at 5 V
4
Maximum Charge Pump Current at 5 V
4
Charge Pump Output Compliance
5
Synthesizer Resolution
CLOCK SYNTHESIZER
CLK Input Frequency
CLK Input Amplitude
Minimum Charge Pump Output Current
4
Maximum Charge Pump Output Current
4
Charge Pump Output Compliance
5
Synthesizer Resolution
Σ-∆ ADC
Resolution
Clock Frequency (f
CLK
)
Center Frequency
Pass-Band Gain Variation
Alias Attenuation
GAIN CONTROL
Programmable Gain Step
AGC Gain Range
GCP Output Resistance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
V
V
IV
IV
IV
IV
IV
VI
VI
VI
IV
IV
IV
VI
VI
VI
VI
IV
IV
V
IV
IV
V
V
IV
Min
Typ
7.5
13
95
−19
−31
−7.0
0.7
500
370||1.4
1
300
2.0
26
3
0.67
5.3
0.4
6.25
13
0.3
0.67
5.3
0.4
2.2
16
13
f
CLK
/8
1.0
80
16
12
72.5
VDDQ − 0.4
VDDP − 0.4
Max
9.5
Unit
dB
dB
dB
dBm
dBm
dBm
dB
MHz
Ω||pF
kΩ
MHz
V p-p
MHz
V p-p
V/µs
mA
mA
V
kHz
MHz
V p-p
mA
mA
V
kHz
Bits
MHz
MHz
dB
dB
dB
dB
kΩ
91
−20
−32
−12
2
300
7.75
0.3
8
0.3
7.5
26
VDDC
24
26
50
95
Rev. A | Page 3 of 47
AD9864
Parameter
OVERALL
Analog Supply Voltage (VDDA, VDDF, VDDI)
Digital Supply Voltage (VDDD, VDDC, VDDL)
Interface Supply Voltage (VDDH)
6
Charge Pump Supply Voltage (VDDP, VDDQ)
Total Current
Operation Mode
7
Standby
OPERATING TEMPERATURE RANGE
1
2
Data Sheet
Temperature
Full
Full
Full
Full
Full
Full
Test Level
VI
VI
VI
VI
VI
VI
−40
Min
2.7
2.7
1.8
2.7
Typ
3.0
3.0
5.0
17
0.01
+85
Max
3.6
3.6
3.6
5.5
Unit
V
V
V
V
mA
mA
°C
This includes 0.9 dB loss of matching network.
AGC with DVGA enabled.
3
Measured in 10 kHz bandwidth.
4
Programmable in 0.67 mA steps.
5
Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
6
VDDH must be less than VDDD + 0.5 V.
7
Clock VCO off and additional 0.7 mA with VGA at maximum attenuation.
Rev. A | Page 4 of 47
Data Sheet
DIGITAL SPECIFICATIONS
AD9864
VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, f
CLK
= 18 MSPS, f
IF
= 109.65 MHz,
f
LO
= 107.4 MHz, f
REF
= 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation setting, synthesizers
in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Table 2.
Parameter
DECIMATOR
Decimation Factor
1
Pass-Band Width
Pass-Band Gain Variation
Alias Attenuation
SPI READ OPERATION (See Figure 30)
PC Clock Frequency
PC Clock Period (t
CLK
)
PC Clock High (t
HI
)
PC Clock Low (t
LOW
)
PC to PD Setup Time (t
DS
)
PC to PD Hold Time (t
DH
)
PE to PC Setup Time (t
S
)
PC to PE Hold Time (t
H
)
SPI WRITE OPERATION
2
(See Figure 29)
PC Clock Frequency
PC Clock Period (t
CLK
)
PC Clock High (t
HI
)
PC Clock Low (t
LOW
)
PC to PD Setup Time (t
DS
)
PC to PD Hold Time (t
DH
)
PC to PD (or DOUTB) Data Valid Time (t
DV
)
PE to PD Output Valid to High-Z (t
EZ
)
SSI
2
(See Figure 33)
CLKOUT Frequency
CLKOUT Period (t
CLK
)
CLKOUT Duty Cycle (t
HI
, t
LOW
)
CLKOUT to FS Valid Time (t
V
)
CLKOUT to DOUT Data Valid Time (t
DV
)
CMOS LOGIC INPUTS
3
Logic 1 Voltage (V
IH
)
Logic 0 Voltage (V
IL
)
Logic 1 Current (I
IH
)
Logic 0 Current (I
IL
)
Input Capacitance
CMOS LOGIC OUTPUTS
2, 3, 4
Logic 1 Voltage (V
OH
)
Logic 0 Voltage (V
OL
)
1
2
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
48
Typ
Max
960
Unit
50%
1.2
88
10
100
45
45
2
2
5
5
10
100
45
45
2
2
3
8
0.867
38.4
33
−1
−1
0.7 × VDDH
0.3 × VDDH
10
10
3
VDDH − 0.2
0.2
26
1153
67
+1
+1
f
CLKOUT
dB
dBm
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
V
V
µA
µA
pF
V
V
50
Programmable in steps of 48 or 60.
CMOS output mode with C
LOAD
= 10 pF and drive strength = 7.
3
Absolute maximum and minimum input/output levels are VDDH + 0.3 V and −0.3 V.
4
I
OL
= 1 mA; specification is also dependent on drive strength setting.
Rev. A | Page 5 of 47
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