Data Sheet
FEATURES
Single-ended-to-differential conversion
Low distortion (V
O, dm
= 40 V p-p)
−99 dBc HD at 100 kHz
Low differential output referred noise: 12 nV/√Hz
High input impedance: 11 MΩ
Fixed gain of 2
No external gain components required
Low output-referred offset voltage: 1.1 mV maximum
Low input bias current: 3.5 μA maximum
Wide supply range
5 V to 26 V
Can produce differential output signals in excess of 40 V p-p
High speed
38 MHz, −3 dB bandwidth at 0.2 V p-p differential output
Fast settling time
200 ns to 0.01% for 12 V step on ±5 V supplies
Disable feature
Available in space-saving, thermally enhanced packages
8-lead, 3 mm × 3 mm LFCSP
8-lead SOIC
Low supply current: I
S
= 10 mA on ±12 V supplies
High Voltage, Differential
18-Bit ADC Driver
ADA4922-1
FUNCTIONAL BLOCK DIAGRAM
ADA4922-1
TOP VIEW
NIC
1
REF
2
V
S+
3
OUT+
4
8
IN
7
DIS
6
V
S–
5
OUT–
05681-001
NOTES
1. EXPOSED PAD MUST BE CONNECTED TO GND.
2. NIC = NO INTERAL CONNECTION.
Figure 1.
The
ADA4922-1
is manufactured on Analog Devices, Inc.,
proprietary, second-generation XFCB process that enables the
amplifier to achieve excellent noise and distortion performance
on high supply voltages.
The
ADA4922-1
is available in an 8-lead 3 mm × 3 mm LFCSP
as well as an 8-lead SOIC package. Both packages are equipped
with an exposed paddle for more efficient heat transfer. The
ADA4922-1
is rated to work over the extended industrial
temperature range, −40°C to +85°C.
–84
–87
–90
R
L
= 2k
SECOND HARMONIC
THIRD HARMONIC
APPLICATIONS
High voltage data acquisition systems
Industrial instrumentation
Spectrum analysis
ATE
Medical instruments
GENERAL DESCRIPTION
The
ADA4922-1
is a differential driver for 16-bit to 18-bit
analog-to-digital converters (ADCs) that have differential input
ranges up to ±20 V. Configured as an easy-to-use, single-ended-
to-differential amplifier, the
ADA4922-1
requires no external
components to drive ADCs. The
ADA4922-1
provides essential
benefits such as low distortion and high SNR that are required
for driving ADCs with resolutions up to 18 bits.
With a wide supply voltage range (5 V to 26 V), high input
impedance, and fixed differential gain of 2, the
ADA4922-1
is
designed to drive ADCs found to in a variety of applications,
including industrial instrumentation.
DISTORTION (dBc)
–93
–96
–99
–102
–105
–108
–111
–114
–117
–120
1
10
FREQUENCY (kHz)
100
V
S
=
12V,
V
O, dm
= 40V p-p
05681-012
V
S
=
5V,
V
O, dm
= 12V p-p
Figure 2. Harmonic Distortion for Various Power Supplies
Rev. A
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ADA4922-1
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Data Sheet
Theory of Operation ...................................................................... 14
Applications Information .............................................................. 16
ADA4922-1 Differential Output Noise Model .......................... 16
Using the REF Pin ...................................................................... 16
Internal Feedback Network Power Dissipation...................... 17
Disable Feature ........................................................................... 17
Driving a Differential Input ADC ............................................ 17
Printed Circuit Board Layout Considerations ....................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/2016—Rev. 0 to Rev. A
Change CP-8-2 to CP-8-13 ........................................... Throughout
Changes to Figure 1 .......................................................................... 1
Changes to Figure 4 .......................................................................... 6
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
10/2005—Revision 0: Initial Version
Rev. A | Page 2 of 19
Data Sheet
SPECIFICATIONS
V
S
= ±12 V, T
A
= 25°C, R
L
= 1 kΩ, DIS = high, C
L
= 3 pF, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Overdrive Recovery Time
Slew Rate
Settling Time to 0.01%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion
Differential Output Voltage Noise
Input Current Noise
DC PERFORMANCE
Differential Output Offset Voltage
Differential Output Offset Voltage Drift
Input Bias Current
Gain
Gain Error
Gain Error Drift
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
DC Output Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Disabled)
Power Supply Rejection Ratio (PSRR)
−PSRR
+PSRR
DISABLE
DIS Input Voltage Threshold
Turn-Off Time
Turn-On Time
DIS Bias Current
Enabled
Disabled
Test Conditions/Comments
G = +2, V
O
= 0.2 V p-p, differential
G = +2, V
O
= 40 V p-p, differential
V
S+
+ 0.5 V to V
S−
− 0.5 V; +recovery/−recovery
V
O, dm
= 2 V step
V
O, dm
= 40 V step
V
O, dm
= 40 V step
f
C
= 5 kHz, V
O
= 40 V p-p, R
L
= 2 kΩ, HD2/HD3
f
C
= 100 kHz, V
O
= 40 V p-p, R
L
= 2 kΩ, HD2/HD3
f = 100 kHz
f = 100 kHz
Min
34
6.5
Typ
38
7.2
180/330
260
730
580
−116/−109
−99/−100
12
1.4
0.35
14
1.8
2
−0.05
0.0002
11
1
±10.7
Each single-ended output, R
L
= 1 kΩ
30% overshoot
5
9.4
1.5
−89
−91
Disabled
Enabled
≤ −11
≥ −9
160
78
114
−125
±10.65
±10.7
40
20
ADA4922-1
Max
Unit
MHz
MHz
ns
V/µs
V/µs
ns
dBc
dBc
nV/√Hz
pA/√Hz
1.1
3.5
mV
µV/°C
µA
V/V
%
%/°C
MΩ
pF
V
V
mA
pF
26
10.1
2.0
−80
−83
V
mA
mA
dB
dB
V
V
µs
ns
µA
µA
DIS = −9 V
DIS = −11 V
Rev. A | Page 3 of 19
ADA4922-1
V
S
= ±5 V, T
A
= 25°C, R
L
= 1 kΩ, DIS = high, C
L
= 3 pF, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Overdrive Recovery Time
Slew Rate
Settling Time to 0.01%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion
Differential Output Voltage Noise
Input Current Noise
DC PERFORMANCE
Differential Output Offset Voltage
Differential Output Offset Voltage Drift
Input Bias Current
Gain
Gain Error
Gain Error Drift
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
DC Output Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Disabled)
Power Supply Rejection Ratio (PSRR)
−PSRR
+PSRR
DISABLE
DIS Input Voltage
Turn-Off Time
Turn-On Time
DIS Bias Current
Enabled
Disabled
Test Conditions/Comments
G = +2, V
O
= 0.2 V p-p, differential
G = +2, V
O
= 12 V p-p, differential
+Recovery/−Recovery
V
O, dm
= 2 V step
V
O, dm
= 12 V step
V
O, dm
= 12 V step
f
C
= 5 kHz, V
O
= 12 V p-p, R
L
= 2 kΩ, HD2/HD3
f
C
= 100 kHz, V
O
= 12 V p-p, R
L
= 2 kΩ, HD2/HD3
f = 100 kHz
f = 100 kHz
Min
36
6.5
Typ
40.5
13.5
200/670
220
350
200
−102/−108
−101/−98
12
1.4
0.4
12
2.0
2
−0.05
0.0002
11
1
±3.6
Each single-ended output, R
L
= 1 kΩ
30% overshoot
5
7.0
0.7
−93
−91
Disabled
Enabled
≤ −4
≥ −2
160
78
41
49
±3.55
±3.6
40
20
Data Sheet
Max
Unit
MHz
MHz
ns
V/µs
V/µs
ns
dBc
dBc
nV/√Hz
pA/√Hz
1.2
3.5
mV
µV/°C
µA
V/V
%
%/°C
MΩ
pF
V
V
mA
pF
26
7.6
1.6
−82
−83
V
mA
mA
dB
dB
V
V
µs
ns
µA
µA
DIS = −2 V
DIS = −4 V
Rev. A | Page 4 of 19
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
26 V
See Figure 3
–65°C to +125°C
–40°C to +85°C
300°C
150°C
ADA4922-1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ
JA
. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θ
JA
.
Figure 3 shows the maximum safe power dissipation in the
packages vs. the ambient temperature for the 8-lead SOIC
(79°C/W) and for the 8-lead LFCSP (81°C/W) on a JEDEC
standard 4-layer board, each with its underside paddle soldered
to a pad that is thermally connected to a PCB plane. θ
JA
values
are approximations.
3.0
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface that is
thermally connected to a copper plane, with zero airflow.
Table 4. Thermal Resistance
Package Type
8-Lead SOIC with EP on 4-Layer Board
8-Lead LFCSP with EP on 4-Layer Board
θ
JA
79
81
θ
JC
25
17
Unit
C/W
C/W
MAXIMUM POWER DISSIPATION (W)
2.5
SOIC
2.0
LFCSP
1.5
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the
ADA4922-1
package is limited by the associated rise in junction temperature
(T
J
) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the
ADA4922-1.
Exceeding a
junction temperature of 150°C for an extended period can
result in changes in the silicon devices potentially causing
failure.
1.0
0.5
05681-041
0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. A | Page 5 of 19
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