S25FL128S/S25FL256S
128 Mb (16 MB)/256 Mb (32 MB)
3.0V SPI Flash Memory
Features
■
■
CMOS 3.0 Volt Core with Versatile I/O
SPI with Multi-I/O
❐
SPI Clock polarity and phase modes 0 and 3
❐
DDR option
❐
Extended Addressing: 24- or 32-bit address options
❐
Serial Command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
❐
Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
❐
Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
❐
AutoBoot - power up or reset and execute a Normal or Quad
read command automatically at a preselected address
❐
Common Flash Interface (CFI) data for configuration infor-
mation.
Programming (1.5 MBps)
❐
256 or 512 Byte Page Programming buffer options
❐
Quad-Input Page Programming (QPP) for slow clock sys-
tems
❐
Automatic ECC-internal hardware Error Correction Code
generation with single bit error correction
Erase (0.5 to 0.65 MBps)
❐
Hybrid sector size option - physical set of thirty two 4-KB
sectors at top or bottom of address space with all remaining
sectors of 64 KB, for compatibility with prior generation S25-
FL devices
❐
Uniform sector option - always erase 256-KB blocks for soft-
ware compatibility with higher density and future devices.
Cycling Endurance
❐
100,000 Program-Erase Cycles, minimum
■
Data Retention
❐
20 Year Data Retention, minimum
Security features
❐
OTP array of 1024 bytes
❐
Block Protection:
• Status Register bits to control protection against program
or erase of a contiguous range of sectors.
• Hardware and software control options
❐
Advanced Sector Protection (ASP)
• Individual sector protection controlled by boot code or
password
Cypress
®
65 nm MirrorBit
®
Technology with Eclipse
™
Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
❐
SO16 and FBGA packages
Temperature Range / Grade:
❐
Industrial (40°C to +85°C)
❐
Industrial Plus (40°C to +105°C)
❐
Automotive AEC-Q100 Grade 3 (40°C to +85°C)
❐
Automotive AEC-Q100 Grade 2 (40°C to +105°C)
❐
Automotive AEC-Q100 Grade 1 (40°C to +125°C)
Packages (all Pb-free)
❐
16-lead SOIC (300 mil)
❐
WSON 6
8 mm
❐
BGA-24 6
8 mm
• 5
5 ball (FAB024) and 4
6 ball (FAC024) footprint
options
• Known Good Die (KGD) and Known Tested Die
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram
CS#
SCK
SI/IO0
SO/IO1
I/O
WP#/IO2
HOLD#/IO3
RESET#
Data Path
Control
Logic
X Decoders
SRAM
MirrorBit Array
Y Decoders
Data Latch
Cypress Semiconductor Corporation
Document Number: 001-98283 Rev. *Q
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 30, 2019
S25FL128S/S25FL256S
Performance Summary
Maximum Read Rates with the Same Core and I/O Voltage (V
IO
= V
CC
= 2.7V to 3.6V)
Command
Read
Fast Read
Dual Read
Quad Read
Clock Rate (MHz)
50
133
104
104
MBps
6.25
16.6
26
52
Maximum Read Rates with Lower I/O Voltage (V
IO
= 1.65V to 2.7V, V
CC
= 2.7V to 3.6V)
Command
Read
Fast Read
Dual Read
Quad Read
Maximum Read Rates DDR (V
IO
= V
CC
= 3V to 3.6V)
Command
Fast Read DDR
Dual Read DDR
Quad Read DDR
Clock Rate (MHz)
80
80
80
MBps
20
40
80
Clock Rate (MHz)
50
66
66
66
MBps
6.25
8.25
16.5
33
Typical Program and Erase Rates
Operation
Page Programming (256-byte page buffer - Hybrid Sector Option)
Page Programming (512-byte page buffer - Uniform Sector Option)
4-KB Physical Sector Erase (Hybrid Sector Option)
64-KB Physical Sector Erase (Hybrid Sector Option)
256-KB Logical Sector Erase (Uniform Sector Option)
KBps
1000
1500
30
500
500
Current Consumption
Operation
Serial Read 50 MHz
Serial Read 133 MHz
Quad Read 104 MHz
Quad DDR Read 80 MHz
Program
Erase
Standby
Current (mA)
16 (max)
33 (max)
61 (max)
90 (max)
100 (max)
100 (max)
0.07 (typ)
Document Number: 001-98283 Rev. *Q
Page 2 of 146
S25FL128S/S25FL256S
Contents
1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
4.3
4.4
4.5
5.
5.1
5.2
5.3
5.4
5.5
6.
6.1
6.2
6.3
Overview
.......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
4
6
7
6.4
7.
7.1
7.2
7.3
7.4
7.5
8.
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
FAC024 24-Ball BGA Package ..................................... 43
Address Space Maps..................................................
45
Overview....................................................................... 45
Flash Memory Array...................................................... 46
ID-CFI Address Space .................................................. 47
OTP Address Space ..................................................... 47
Registers....................................................................... 49
Data Protection
........................................................... 58
Secure Silicon Region (OTP)........................................ 58
Write Enable Command................................................ 58
Block Protection ............................................................ 59
Advanced Sector Protection ......................................... 60
Commands
.................................................................. 64
Command Set Summary............................................... 65
Identification Commands .............................................. 70
Register Access Commands......................................... 72
Read Memory Array Commands .................................. 82
Program Flash Array Commands ................................. 98
Erase Flash Array Commands.................................... 105
One Time Program Array Commands ........................ 110
Advanced Sector Protection Commands .................... 111
Reset Commands ....................................................... 117
Embedded Algorithm Performance Tables ................. 118
Software Interface
Hardware Interface
Signal Descriptions
..................................................... 8
Input/Output Summary................................................... 8
Address and Data Configuration.................................... 9
RESET# ......................................................................... 9
Serial Clock (SCK) ......................................................... 9
Chip Select (CS#) .......................................................... 9
Serial Input (SI) / IO0 ..................................................... 9
Serial Output (SO) / IO1............................................... 10
Write Protect (WP#) / IO2 ............................................ 10
Hold (HOLD#) / IO3 ..................................................... 10
Core Voltage Supply (V
CC
) .......................................... 11
Versatile I/O Power Supply (V
IO
) ................................. 11
Supply and Signal Ground (V
SS
) ................................. 11
Not Connected (NC) .................................................... 11
Reserved for Future Use (RFU)................................... 11
Do Not Use (DNU) ....................................................... 11
Block Diagrams............................................................ 12
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Thermal Resistance .....................................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics ..............................................
Physical Interface
......................................................
SOIC 16-Lead Package ...............................................
WSON Package...........................................................
FAB024 24-Ball BGA Package ....................................
13
13
14
17
22
22
23
23
23
23
24
26
28
28
28
29
31
35
37
37
39
41
10. Data Integrity
............................................................. 120
10.1 Erase Endurance ........................................................ 120
10.2 Data Retention ............................................................ 120
11. Software Interface Reference
.................................. 121
11.1 Command Summary ................................................... 121
11.2 Device ID and Common Flash Interface
(ID-CFI) Address Map................................................. 123
11.3 Device ID and Common Flash Interface
(ID-CFI) ASO Map — Automotive Only ...................... 136
11.4 Registers..................................................................... 136
11.5 Initial Delivery State .................................................... 139
12.
Ordering Information
................................................ 140
13. Revision History........................................................
142
Sales, Solutions, and Legal Information ........................ 146
Worldwide Sales and Design Support ......................... 146
Products ...................................................................... 146
PSoC® Solutions ........................................................ 146
Cypress Developer Community ................................... 146
Technical Support ....................................................... 146
Document Number: 001-98283 Rev. *Q
Page 3 of 146
S25FL128S/S25FL256S
1. Overview
1.1 General Description
The Cypress S25FL128S and S25FL256S devices are flash non-volatile memory products using:
■
■
■
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
This family of devices connect to a host system via a SPI. Traditional SPI single bit serial input and output (Single I/O or SIO) is
supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface
is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer
address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be
programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase
algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface,
asynchronous, NOR flash memories while reducing signal count dramatically.
The S25FL128S and S25FL256S products offer high densities coupled with the flexibility and fast performance required by a variety
of embedded applications. They are ideal for code shadowing, XIP, and data storage.
1.2 Migration Notes
1.2.1
Features Comparison
The S25FL128S and S25FL256S devices are command set and footprint compatible with prior generation FL-K and FL-P families.
Table 1. FL Generations Comparison
[1, 2, 3, 4, 5]
Parameter
Technology Node
Architecture
Release Date
Density
Bus Width
Supply Voltage
Normal Read Speed (SDR)
Fast Read Speed (SDR)
Dual Read Speed (SDR)
Quad Read Speed (SDR)
Fast Read Speed (DDR)
Dual Read Speed (DDR)
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector Size
Parameter Sector Size
FL-K
90 nm
Floating Gate
In Production
4 Mb - 128 Mb
x1, x2, x4
2.7V - 3.6V
6 MBps (50 MHz)
13 MBps (104 MHz)
26 MBps (104 MHz)
52 MBps (104 MHz)
–
–
–
256B
4 KB / 32 KB / 64 KB
4 KB
FL-P
90 nm
MirrorBit
In Production
32 Mb - 256 Mb
x1, x2, x4
2.7V - 3.6V
5 MBps (40 MHz)
13 MBps (104 MHz)
20 MBps (80 MHz)
40 MBps (80 MHz)
–
–
–
256B
64 KB / 256 KB
4 KB
FL-S
65 nm
MirrorBit Eclipse
2H2011
128 Mb - 256 Mb
x1, x2, x4
2.7V - 3.6V / 1.65V - 3.6V V
IO
6 MBps (50 MHz)
17 MBps (133 MHz)
26 MBps (104 MHz)
52 MBps (104 MHz)
20 MBps (80 MHz)
40 MBps (80 MHz)
80 MBps (80 MHz)
256B / 512B
64 KB / 256 KB
4 KB (option)
Notes
1. 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density).
3. 64-KB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.
4. FL-K family devices can erase 4-KB sectors in groups of 32 KB or 64 KB.
5. Refer to individual datasheets for further details.
Document Number: 001-98283 Rev. *Q
Page 4 of 146
S25FL128S/S25FL256S
Table 1. FL Generations Comparison
[1, 2, 3, 4, 5]
(Continued)
Parameter
Sector Erase Time (typ.)
Page Programming Time (typ.)
OTP
Advanced Sector Protection
Auto Boot Mode
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
FL-K
30 ms (4 KB), 150 ms (64 KB)
700 µs (256B)
768B (3 x 256B)
No
No
Yes
Yes
40°C
to +85°C
FL-P
500 ms (64 KB)
1500 µs (256B)
506B
No
No
No
No
40°C
to +85°C / +105°C
FL-S
130 ms (64 KB), 520 ms (256
KB)
250 µs (256B), 340 µs (512B)
1024B
Yes
Yes
Yes
Yes
40°C
to +85°C /
+105°C / +125°C
Notes
1. 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density).
3. 64-KB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.
4. FL-K family devices can erase 4-KB sectors in groups of 32 KB or 64 KB.
5. Refer to individual datasheets for further details.
1.2.2
Known Differences from Prior Generations
1.2.2.1 Error Reporting
Prior generation FL memories either do not have error status bits or do not set them if program or erase is attempted on a protected
sector. The FL-S family does have error reporting status bits for program and erase operations. These can be set when there is an
internal failure to program or erase or when there is an attempt to program or erase a protected sector. In either case, the program
or erase operation did not complete as requested by the command.
1.2.2.2 Secure Silicon Region (OTP)
The size and format (address map) of the OTP area is different from prior generations. The method for protecting each portion of the
OTP area is different. For additional details, see
Section 8.1 Secure Silicon Region (OTP) on page 58.
1.2.2.3 Configuration Register Freeze Bit
The Configuration Register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior generations. In the FL-S family,
it also locks the state of the Configuration Register TBPARM bit CR1[2], TBPROT bit CR1[5], and the Secure Silicon Region (OTP)
area.
1.2.2.4 Sector Erase Commands
The command for erasing an 8-KB area (two 4-KB sectors) is not supported.
The command for erasing a 4-KB sector is supported only in the 128-Mb and 256-Mb density FL-S devices and only for use on the
thirty two 4-KB parameter sectors at the top or bottom of the device address space.
The erase command for 64-KB sectors are supported for the 128-Mb and 256-Mb density FL-S devices when the ordering option for
4-KB parameter sectors with 64-KB uniform sectors are used. The 64-KB erase command may be applied to erase a group of
sixteen 4-KB sectors.
The erase command for a 256-KB sector replaces the 64-KB erase command when the ordering option for 256-KB uniform sectors
is used for the 128-Mb and 256-Mb density FL-S devices.
Document Number: 001-98283 Rev. *Q
Page 5 of 146
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