1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
The SST39LF010, SST39LF020, SST39LF040 and SST39VF010, SST39VF020,
SST39VF040 are 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash
(MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide tunneling injector attain bet-
ter reliability and manufacturability compared with alternate approaches. The
SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power
supply. The SST39VF010/020/040 devices write with a 2.7-3.6V power supply.
The devices conform to JEDEC standard pinouts for x8 memories.
Features
• Organized as 128K x8 / 256K x8 / 512K x8
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF010/020/040
– 2.7-3.6V for SST39VF010/020/040
• Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
2 seconds (typical) for SST39LF/VF010
4 seconds (typical) for SST39LF/VF020
8 seconds (typical) for SST39LF/VF040
• Automatic Write Timing
– Internal V
PP
Generation
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 1 µA (typical)
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• Sector-Erase Capability
– Uniform 4 KByte sectors
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Fast Read Access Time:
– 55 ns for SST39LF010/020/040
– 70 ns for SST39VF010/020/040
• Latched Address and Data
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
• All devices are RoHS compliant
©2012 Silicon Storage Technology, Inc.
www.microchip.com
DS25023B
06/13
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Product Description
The SST39LF010, SST39LF020, SST39LF040 and SST39VF010, SST39VF020, SST39VF040 are
128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprie-
tary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tun-
neling injector attain better reliability and manufacturability compared with alternate approaches. The
SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The
SST39VF010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC
standard pinouts for x8 memories.
Featuring high performance Byte-Program, the SST39LF010/020/040 and SST39VF010/020/040
devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data#
Polling to indicate the completion of Program operation. To protect against inadvertent write, they have
on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a
wide spectrum of applications, they are offered with a guaranteed typical endurance of 100,000 cycles.
Data retention is rated at greater than 100 years.
The SST39LF010/020/040 and SST39VF010/020/040 devices are suited for applications that require
convenient and economical updating of program, configuration, or data memory. For all system appli-
cations, they significantly improves performance and reliability, while lowering power consumption.
They inherently use less energy during Erase and Program than alternative flash technologies. The
total energy consumed is a function of the applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or Program operation is less than alternative
flash technologies. These devices also improve flexibility while lowering the cost for program, data, and
configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39LF010/020/040 and SST39VF010/020/040 devices
are offered in 32-lead PLCC and 32-lead TSOP packages. See Figures 2 and 3 for pin assignments.
©2012 Silicon Storage Technology, Inc.
DS25023B
06/13
2
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Block Diagram
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffers & Latches
Y-Decoder
CE#
OE#
WE#
Control Logic
I/O Buffers and Data Latches
DQ
7
- DQ
0
1150 B1.1
Figure 1:
Functional Block Diagram
©2012 Silicon Storage Technology, Inc.
DS25023B
06/13
3
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Pin Assignments
SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
WE#
WE#
WE#
VDD
A12
A15
A16
A18
VDD
A12
A15
A16
VDD
A12
A15
A16
NC
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010
NC
A17
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
4
3
2
1
32 31 30
29
28
27
26
25
24
23
22
SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
32-lead PLCC
Top View
21
14 15 16 17 18 19 20
1150 32-plcc NH P4.4
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ5
DQ5
DQ1
DQ2
VSS
DQ3
DQ4
DQ1
DQ2
VSS
DQ3
DQ4
Figure 2:
Pin Assignments for 32-lead PLCC
©2012 Silicon Storage Technology, Inc.
DQ6
DQ6
DQ6
DS25023B
06/13
4
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010
A11
A9
A8
A13
A14
A17
WE#
VDD
A18
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1150 32-tsop WH P1.1
SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Standard Pinout
Top View
Die Up
Figure 3:
Pin Assignments for 32-lead TSOP (8mm x 14mm)
Table 1:
Pin Description
Symbol
A
MS1
-A
0
DQ
7
-DQ
0
Pin Name
Address Inputs
Functions
To provide memory addresses. During Sector-Erase A
MS
-A
12
address lines will
select the sector. During Block-Erase A
MS
-A
16
address lines will select the block.
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
Chip Enable
To activate the device when CE# is low.
Output Enable
To gate the data output buffers.
Write Enable
To control the Write operations.
Power Supply
To provide power supply voltage:
3.0-3.6V for SST39LF010/020/040
2.7-3.6V for SST39VF010/020/040
Ground
No Connection
Unconnected pins.
T1.1 25023
CE#
OE#
WE#
V
DD
V
SS
NC
1. A
MS
= Most significant address
A
MS
= A
16
for SST39LF/VF010, A
17
for SST39LF/VF020, and A
18
for SST39LF/VF040
©2012 Silicon Storage Technology, Inc.
DS25023B
06/13
5
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