MT47H32M16NF-25E:H datasheet, PDF

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MT47H32M16NF-25E:H: DescriptionDDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, FBGA-84; Categorystorage; File Size2MB，133 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT47H32M16NF-25E:H Overview

DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, FBGA-84

MT47H32M16NF-25E:H Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	BGA
package instruction	TFBGA, BGA84,9X15,32
Contacts	84
Reach Compliance Code	not_compliant
ECCN code	EAR99
Factory Lead Time	7 weeks
Is Samacsys	N
access mode	FOUR BANK PAGE BURST
Maximum access time	0.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	400 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B84
JESD-609 code	e1
length	12.5 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	84
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	32MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA84,9X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	4,8
Maximum standby current	0.01 A
Maximum slew rate	0.215 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm
Base Number Matches	1

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512Mb: x4, x8, x16 DDR2 SDRAM

Features

DDR2 SDRAM

MT47H128M4 – 32 Meg x 4 x 4 banks

MT47H64M8 – 16 Meg x 8 x 4 banks

MT47H32M16 – 8 Meg x 16 x 4 banks

Features

•

= 1.8V ±0.1V, V

DDQ

= 1.8V ±0.1V

JEDEC-standard 1.8V I/O (SSTL_18-compatible)

Differential data strobe (DQS, DQS#) option

4n-bit prefetch architecture

Duplicate output strobe (RDQS) option for x8

DLL to align DQ and DQS transitions with CK

4 internal banks for concurrent operation

Programmable CAS latency (CL)

Posted CAS additive latency (AL)

WRITE latency = READ latency - 1

Selectable burst lengths: 4 or 8

Adjustable data-output drive strength

64ms, 8192-cycle refresh

On-die termination (ODT)

Industrial temperature (IT) option

RoHS-compliant

Supports JEDEC clock jitter specification

Options

• Configuration

– 128 Meg x 4 (32 Meg x 4 x 4 banks)

– 64 Meg x 8 (16 Meg x 8 x 4 banks)

– 32 Meg x 16 (8 Meg x 16 x 4 banks)

• FBGA package (Pb-free) – x16

– 84-ball FBGA (8mm x 12.5mm) Rev. G

– 84-ball FBGA (8mm x 12.5mm) Rev. H

• FBGA package (Pb-free) – x4, x8

– 60-ball FBGA (8mm x 10mm) Rev. G

– 60-ball FBGA (8mm x 10mm) Rev. H

• FBGA package (lead solder) – x16

– 84-ball FBGA (8mm x 12.5mm) Rev. G

• FBGA package (lead solder) – x4, x8

– 60-ball FBGA (8mm x 10mm) Rev. G

• Timing – cycle time

– 1.875ns @ CL = 7 (DDR2-1066)

– 2.5ns @ CL = 5 (DDR2-800)

– 3.0ns @ CL = 5 (DDR2-667)

• Self refresh

– Standard

– Low-power

• Operating temperature

– Commercial (0°C

≤

+85°C)

– Industrial (–40°C

≤

+95°C;

–40°C

≤

+85°C)

• Revision

Notes:

Marking

128M4

64M8

32M16

-187E

-25E

-3

None

:G/:H

1. Not all options listed can be combined to

define an offered product. Use the Part

Catalog Search on

www.micron.com

for

product offerings and availability.

2. For extended CT operating temperature,

see Table 11 (page 29), Note 7.

Table 1: Key Timing Parameters

Data Rate (MT/s)

Speed Grade

-187E

-25E

-3

CL = 3

400

CL = 4

533

CL = 5

800

667

CL = 6

800

n/a

CL = 7

1066

n/a

(ns)

PDF: 09005aef85651470

512MbDDR2.pdf - Rev. Y 06/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Features

Contents

State Diagram .................................................................................................................................................. 8

Functional Description ..................................................................................................................................... 9

Industrial Temperature ................................................................................................................................. 9

General Notes ............................................................................................................................................ 10

Functional Block Diagrams ............................................................................................................................. 11

Ball Assignments and Descriptions ................................................................................................................. 13

Packaging ...................................................................................................................................................... 17

Package Dimensions ................................................................................................................................... 17

FBGA Package Capacitance ......................................................................................................................... 21

Electrical Specifications – Absolute Ratings ..................................................................................................... 22

Temperature and Thermal Impedance ........................................................................................................ 22

Electrical Specifications – I

Parameters ........................................................................................................ 25

Specifications and Conditions ............................................................................................................... 25

DD7

Conditions .......................................................................................................................................... 25

AC Timing Operating Specifications ................................................................................................................ 32

AC and DC Operating Conditions .................................................................................................................... 44

ODT DC Electrical Characteristics ................................................................................................................... 44

Input Electrical Characteristics and Operating Conditions ............................................................................... 45

Output Electrical Characteristics and Operating Conditions ............................................................................. 48

Output Driver Characteristics ......................................................................................................................... 50

Power and Ground Clamp Characteristics ....................................................................................................... 54

AC Overshoot/Undershoot Specification ......................................................................................................... 55

Input Slew Rate Derating ................................................................................................................................ 57

Commands .................................................................................................................................................... 70

Truth Tables ............................................................................................................................................... 70

DESELECT ................................................................................................................................................. 74

NO OPERATION (NOP) ............................................................................................................................... 75

LOAD MODE (LM) ...................................................................................................................................... 75

ACTIVATE .................................................................................................................................................. 75

READ ......................................................................................................................................................... 75

WRITE ....................................................................................................................................................... 75

PRECHARGE .............................................................................................................................................. 76

REFRESH ................................................................................................................................................... 76

SELF REFRESH ........................................................................................................................................... 76

Mode Register (MR) ........................................................................................................................................ 76

Burst Length .............................................................................................................................................. 77

Burst Type .................................................................................................................................................. 78

Operating Mode ......................................................................................................................................... 78

DLL RESET ................................................................................................................................................. 78

Write Recovery ........................................................................................................................................... 79

Power-Down Mode ..................................................................................................................................... 79

CAS Latency (CL) ........................................................................................................................................ 80

Extended Mode Register (EMR) ....................................................................................................................... 81

DLL Enable/Disable ................................................................................................................................... 82

Output Drive Strength ................................................................................................................................ 82

DQS# Enable/Disable ................................................................................................................................. 82

RDQS Enable/Disable ................................................................................................................................. 82

Output Enable/Disable ............................................................................................................................... 82

On-Die Termination (ODT) ......................................................................................................................... 83

Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 83

PDF: 09005aef85651470

512MbDDR2.pdf - Rev. Y 06/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Features

Posted CAS Additive Latency (AL) ................................................................................................................ 83

Extended Mode Register 2 (EMR2) ................................................................................................................... 85

Extended Mode Register 3 (EMR3) ................................................................................................................... 86

Initialization .................................................................................................................................................. 87

ACTIVATE ...................................................................................................................................................... 90

READ ............................................................................................................................................................. 92

READ with Precharge .................................................................................................................................. 96

READ with Auto Precharge .......................................................................................................................... 98

WRITE .......................................................................................................................................................... 103

PRECHARGE ................................................................................................................................................. 113

REFRESH ...................................................................................................................................................... 114

SELF REFRESH .............................................................................................................................................. 115

Power-Down Mode ........................................................................................................................................ 117

Precharge Power-Down Clock Frequency Change ........................................................................................... 124

Reset ............................................................................................................................................................. 125

CKE Low Anytime ...................................................................................................................................... 125

ODT Timing .................................................................................................................................................. 127

MRS Command to ODT Update Delay ........................................................................................................ 129

PDF: 09005aef85651470

512MbDDR2.pdf - Rev. Y 06/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Features

List of Figures

Figure 1: 512Mb DDR2 Part Numbers ............................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................... 8

Figure 3: 128 Meg x 4 Functional Block Diagram ............................................................................................. 11

Figure 4: 64 Meg x 8 Functional Block Diagram ............................................................................................... 12

Figure 5: 32 Meg x 16 Functional Block Diagram ............................................................................................. 12

Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 13

Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 14

Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16; Die Rev. :G .............................................................................. 17

Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8; Die Rev. :G ............................................................................. 18

Figure 10: 84-Ball FBGA (8mm x 12.5mm) – x16; "NF" Die Rev. :H .................................................................... 19

Figure 11: 60-Ball FBGA (8mm x 10mm) – x4, x8; "SH" Die Rev. :H ................................................................... 20

Figure 12: Example Temperature Test Point Location ...................................................................................... 23

Figure 13: Single-Ended Input Signal Levels ................................................................................................... 45

Figure 14: Differential Input Signal Levels ...................................................................................................... 46

Figure 15: Differential Output Signal Levels .................................................................................................... 48

Figure 16: Output Slew Rate Load .................................................................................................................. 49

Figure 17: Full Strength Pull-Down Characteristics ......................................................................................... 50

Figure 18: Full Strength Pull-Up Characteristics .............................................................................................. 51

Figure 19: Reduced Strength Pull-Down Characteristics .................................................................................. 52

Figure 20: Reduced Strength Pull-Up Characteristics ...................................................................................... 53

Figure 21: Input Clamp Characteristics .......................................................................................................... 54

Figure 22: Overshoot ..................................................................................................................................... 55

Figure 23: Undershoot ................................................................................................................................... 55

Figure 24: Nominal Slew Rate for

IS ............................................................................................................... 60

Figure 25: Tangent Line for

IS ........................................................................................................................ 60

Figure 26: Nominal Slew Rate for

IH .............................................................................................................. 61

Figure 27: Tangent Line for

IH ....................................................................................................................... 61

Figure 28: Nominal Slew Rate for

DS ............................................................................................................. 66

Figure 29: Tangent Line for

DS ...................................................................................................................... 66

Figure 30: Nominal Slew Rate for

DH ............................................................................................................. 67

Figure 31: Tangent Line for

DH ..................................................................................................................... 67

Figure 32: AC Input Test Signal Waveform Command/Address Balls ................................................................ 68

Figure 33: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 68

Figure 34: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 69

Figure 35: AC Input Test Signal Waveform (Differential) .................................................................................. 69

Figure 36: MR Definition ............................................................................................................................... 77

Figure 37: CL ................................................................................................................................................. 80

Figure 38: EMR Definition ............................................................................................................................. 81

Figure 39: READ Latency ............................................................................................................................... 84

Figure 40: WRITE Latency .............................................................................................................................. 84

Figure 41: EMR2 Definition ........................................................................................................................... 85

Figure 42: EMR3 Definition ........................................................................................................................... 86

Figure 43: DDR2 Power-Up and Initialization ................................................................................................. 87

Figure 44: Example: Meeting

RRD (MIN) and

RCD (MIN) .............................................................................. 90

Figure 45: Multibank Activate Restriction ....................................................................................................... 91

Figure 46: READ Latency ............................................................................................................................... 93

Figure 47: Consecutive READ Bursts .............................................................................................................. 94

Figure 48: Nonconsecutive READ Bursts ........................................................................................................ 95

Figure 49: READ Interrupted by READ ............................................................................................................ 96

Figure 50: READ-to-WRITE ............................................................................................................................ 96

PDF: 09005aef85651470

512MbDDR2.pdf - Rev. Y 06/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT47H32M16NF-25E:H Related Products

	MT47H32M16NF-25E:H	MT47H32M16HR-25E:G	MT47H64M8JN-25E:G	MT47H32M16HR-3:G	MT47H32M16HW-25E:G
Description	DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, FBGA-84	DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84	DDR DRAM, 64MX8, 0.4ns, CMOS, PBGA60, 8 X 10 MM, FBGA-60	DDR DRAM, 32MX16, 0.45ns, CMOS, PBGA84, 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84	DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, FBGA-84
Is it lead-free?	Lead free	Lead free	Contains lead	Lead free	Contains lead
Is it Rohs certified?	conform to	conform to	incompatible	conform to	incompatible
Maker	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology
Parts packaging code	BGA	BGA	BGA	BGA	BGA
package instruction	TFBGA, BGA84,9X15,32	TFBGA, BGA84,9X15,32	TFBGA, BGA60,9X11,32	TFBGA, BGA84,9X15,32	8 X 12.50 MM, FBGA-84
Contacts	84	84	60	84	84
Reach Compliance Code	not_compliant	compliant	not_compliant	compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.4 ns	0.4 ns	0.4 ns	0.45 ns	0.4 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	400 MHz	400 MHz	400 MHz	333 MHz	400 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	4,8	4,8	4,8	4,8	4,8
JESD-30 code	R-PBGA-B84	R-PBGA-B84	R-PBGA-B60	R-PBGA-B84	R-PBGA-B84
JESD-609 code	e1	e1	e0	e1	e0
length	12.5 mm	12.5 mm	10 mm	12.5 mm	12.5 mm
memory density	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	16	8	16	16
Number of functions	1	1	1	1	1
Number of ports	1	1	1	1	1
Number of terminals	84	84	60	84	84
word count	33554432 words	33554432 words	67108864 words	33554432 words	33554432 words
character code	32000000	32000000	64000000	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
organize	32MX16	32MX16	64MX8	32MX16	32MX16
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA84,9X15,32	BGA84,9X15,32	BGA60,9X11,32	BGA84,9X15,32	BGA84,9X15,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260	235	260	235
power supply	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES
Continuous burst length	4,8	4,8	4,8	4,8	4,8
Maximum standby current	0.01 A	0.007 A	0.007 A	0.007 A	0.007 A
Maximum slew rate	0.215 mA	0.215 mA	0.215 mA	0.215 mA	0.215 mA
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal surface	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead/Silver (Sn/Pb/Ag)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead/Silver (Sn/Pb/Ag)
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	30	30	30
width	8 mm	8 mm	8 mm	8 mm	8 mm
Base Number Matches	1	1	1	-	-

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