IBM025160LG5D-60 datasheet, PDF

Datasheet> All Categories > storage> IBM025160LG5D-60

IBM025160LG5D-60: DescriptionVideo DRAM, 256KX16, 60ns, CMOS, PDSO64, 0.472 INCH, SSOG-64; Categorystorage; File Size592KB，65 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

Download Datasheet Parametric View All

IBM025160LG5D-60 Overview

Video DRAM, 256KX16, 60ns, CMOS, PDSO64, 0.472 INCH, SSOG-64

IBM025160LG5D-60 Parametric

Parameter Name	Attribute value
Maker	IBM
Parts packaging code	SOIC
package instruction	SSOP, SOP64,.54,32
Contacts	64
Reach Compliance Code	unknown
ECCN code	EAR99
Is Samacsys	N
access mode	FAST PAGE
Maximum access time	60 ns
Other features	RAS ONLY/CAS BEFORE RAS REFRESH
JESD-30 code	R-PDSO-G64
length	26.3 mm
memory density	4194304 bit
Memory IC Type	VIDEO DRAM
memory width	16
Number of functions	1
Number of ports	2
Number of terminals	64
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SOP64,.54,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
power supply	5 V
Certification status	Not Qualified
refresh cycle	512
Maximum seat height	2.38 mm
Maximum standby current	0.005 A
Maximum slew rate	0.16 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	12 mm
Base Number Matches	1

Preview

Download Datasheet

View All

IBM025160256 x 16FP, 2CE. IBM025171256 x 16EDO, 2WE. IBM025170256 x 16FP, 2WE. IBM025161256 x 16EDO, 2CE.

IBM025160 IBM025170

IBM025161 IBM025171

256K X 16 MULTIPORT VIDEO RAM

Features

• 256K x 16 Multiport Video RAM

• Performance:

Parameter

SCA

CAC

SCC

HPC

-6H

25ns

12ns

15ns

25ns

12ns

95ns

30ns

20ns

-60

25ns

15ns

30ns

18ns

95ns

30ns

25ns

-70

30ns

17ns

• 50 MHz EDO performance

• FLASH WRITE with WPBM- 512 x 16 bits

• Persistent & Non-Persistent WPBM mode

• Split Serial Register with Width Control

• 256 Location Start Address Pointer for SAM

17ns

35ns

20ns

110ns

40ns

30ns

Precharge

Serial Access Time

Access Time from

Column Address Access Time

Serial Clock Cycle Time

Read or Write Cycle Time

Fast Page Mode Cycle Time

Extended Data Out Cycle Time

• Full Read and Split Read Transfer

• Masked Write Transfer

• Masked Split Write Transfer

• Power Supply: 5.0V

0.5V and 3.3V

0.3V

• High Performance, CMOS 0.55µm process

• Fully Asynchronous operation of Random port

and Serial port

• Compatible to Full Depth SAM in SRS mode

• 8 Column Block Write with masking Column and

WPB masking along with individual Byte Control

• SSOG-64 JEDEC Standard

• TTL compatible

Description

This 4Mb dual port Video RAM (VRAM) consists of a

Dynamic Random Access Memory (DRAM) orga-

nized as 256K x 16 interfaced to a Serial Register /

Serial Access Memory (SAM) organized as 256 x

16. The VRAM supports three basic operations:

Bidirectional Random Access to the DRAM, Bidirec-

tional Serial Access to the SAM, and Bidirectional

Data Transfer between any DRAM row and the

SAM. Full compatibility is provided between Half

Depth SAM (256 x 16) and Full Depth SAM (512 x

16) by setting the VRAM in Serial Register Stop

(SRS) mode with a stop address of 128 bit (or less).

Unique features have been added to these basic

VRAM operations to improve graphics performance

of the system. Higher update rates can be achieved

with either Flash Write or Block Write modes. Two

or two

inputs are provided for individual byte con-

trol for both normal Write and Block Write. For indi-

vidual bit control, a Write-Per-Bit Mask (WPBM) can

be supplied on the data pins at

time to be used

during Masked Write transfers or Masked Write

cycles. A permanent mask to be used during Block

Write cycles can be loaded using the Load Mask

33G0307

SA14-4751-05

Revised 3/98

Use is further subject to the provisions at the end of this document.

Page 1 of 65

IBM025160 IBM025170

IBM025161 IBM025171

256K X 16 MULTIPORT VIDEO RAM

Detailed Pin Description

RE - Row Enable; also known as RAS

This pin is functionally equivalent to a chip enable signal in that whenever it is activated, 8192 storage cells of

the selected row are sensed simultaneously and the sense amplifiers restore all data. The falling edge of RE

latches data on address pins A

-A

. CE, TRG, W, and DSF are simultaneously latched to invoke the DRAM

port and Serial port operations.

CE - Column Enable (Dual WE parts only); also known as CAS.

This pin serves as a chip select signal. It activates the column decoder and the I/O buffer. The falling edge of

CE latches the column address A

-A

. State of DSF at falling edge of CE invokes various DRAM port and

Serial port functions.

LCE, UCE - Lower and Upper Column Enable (Dual CE parts only).

These pins enable lower and upper byte respectively of the selected column for Read/Write. The falling edge

of either LCE or UCE latches the column address and state of DSF to invoke various DRAM port and Serial

port functions.

W - Write (Dual CE parts only)

This pin enables the DRAM port write circuitry. It is also used as a control input pin to define the various oper-

ations at RE fall time.

LW, UW - Lower and Upper Write (Only in Dual W parts)

These pins enable the DRAM port write circuitry for Lower and Upper Byte Write respectively. Either LW or

UW being low is considered low for Write cycles.

TRG - Data Transfer and Output Enable (DT/OE)

This is a multifunctional input pin. In conjunction with LW/UW, DSF and CE, it either enables the DRAM data

outputs or enables transfer operations between DRAM and SAM. This is also used as a control input pin to

define the various operating modes at RE time.

DSF - Designated Special Function

A control pin used in conjunction with other control pins to define the various operating modes at RE and CE

time.

- A

- Address Inputs

These pins are multiplexed as row and column address inputs. Row addresses are first used to select one of

the possible 512 rows for a Read, Write, Data Transfer, or Refresh cycles. Column addresses are then sup-

plied to select one of the possible 512 columns for a Read or a Write cycle or one of the possible 256 starting

locations for the next Serial Read/Write cycle for the Serial port.

33G0307

SA14-4751-05

Revised 3/98

Use is further subject to the provisions at the end of this document.

Page 3 of 65

IBM025170 IBM025160

IBM025171 IBM025161

256K X 16 MULTIPORT VIDEO RAM

- DQ

- Random Port Data Input/Output

In a Read cycle, these pins serve as outputs for the selected storage cells. In a Write cycle, data input on

these pins is latched by the falling edge of CE or LW/UW whichever occurs later. Data will not appear at the

outputs until after both CE and TRG have been brought low. During transfer operations, the DQ outputs

remain in the high-Z state for the entire cycle. In a Block Write cycle, data input on these pins is used to mask

the selected columns in the block. At RE falling edge, the data input at these pins can be used for loading the

Write-per-Bit Mask (WPBM).

SDQ

- SDQ

- Serial Port Data Input/Output

16 bit data can be written or read from these pins. The output data remains valid until the next SC clock is

activated.

SC - Serial Clock

The rising edge of the SC signal is used to initiate a Read/Write from/to the SAM Register (starting from the

location specified in the data transfer cycle). In the Serial Read mode, 16 of the 4096 data bits from the SAM

latched on the rising edge of SC clock. Whenever SC clock is low, the Serial port is in standby.

SE - Serial Port Enable

This signal enables or disables the Serial Input/Output buffer. When SE is high, the output of the Serial port is

in tri-state.

While SE is held high, the serial clock is not disabled. Thus, external SC pulses will incre-

ment the internal Serial address counter regardless of the state of SE. This ungated serial clock

scheme minimizes access time of Serial output from SE low since the Serial Clock input buffer and

the Serial address counter are not disabled by SE.

- (5.0V

0.5V) or (3.3V

0.3V) voltage.

All voltages are referenced to the nearest V

pin.

- Circuit ground. V

= 0V.

NC - No Connect.

NC implies that the pin(s) should not be grounded or connected to any other signal. These pins might be used

for testing some modes at factory. Consult factory before using any one of NC pins.

Use is further subject to the provisions at the end of this document.

33G0307

SA14-4751-05

Revised 3/98

Page 4 of 65

Recommended Resources

Regarding the power supply design part of DDR, it is worth collecting!

Photoelectric control bird song circuit

3V regulated power supply circuit

Music hold circuit circuit diagram

Low dropout voltage stabilization circuit diagram

Adjustable gain amplifier circuit

dsp5502 uart communication based on mcbsp: Why does it say I have unresolved symbols even though I defined the header file? What should I add to the File Search Path?...; -Lee- DSP and ARM Processors

Help, about F5438: I run Fast Fourier Transform (FFT) on 5438. It works fine with 512 points, but when I change it to 1024 points, the program automatically runs as soon as it enters the video. It can be paused. I run i...; DHCJOHN Microcontroller MCU

What is a car audio system? Five key points of car audio technology: 1. Composition and structure The most basic condition for an audio system to be called an audio system is that it has the function of playing back sound. In an audio system, at least the following poi...; Jacktang Analogue and Mixed Signal

How to test the performance parameters of op amps, such as bandwidth, noise and slew rate?: I want to check if the parameters of an op amp are consistent with those in the manual, but I don't know how to measure the bandwidth noise and slew rate of an op amp? Has anyone tested it before? Can...; zk643 Analog electronics

【MP430 Sharing】Design and implementation of vibration monitoring system based on wireless network: This paper introduces the design of a wireless sensor network node based on the vibration sensor ADXL 105. The hardware composition and software implementation of the node are introduced in detail. Th...; 鑫海宝贝 Microcontroller MCU

Application of Dacai UART screen in air detector: Over the years, while the local economy has developed rapidly, various regions have continued to experience varying degrees of environmental pollution incidents such as water, air, and noise, which ha...; dcolour2019 MCU

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components