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2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output
8-Bit DAC in a SOT-23
AD5300
FEATURES
Single 8-Bit DAC
6-Lead SOT-23 and 8-Lead MSOP Packages
Micropower Operation: 140 μA @ 5 V
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
2.7 V to 5.5 V Power Supply
Guaranteed Monotonic by Design
Reference Derived from Power Supply
Power-On Reset to 0 V
3 Power-Down Functions
Low Power Serial Interface with Schmitt-Triggered Inputs
On-Chip Output Buffer Amplifier, Rail-to-Rail Operation
SYNC Interrupt Facility
Qualified for automotive applications
FUNCTIONAL BLOCK DIAGRAM
V
DD
POWER-ON
RESET
REF (+) REF (–)
8-BIT
DAC
GND
AD5300
OUTPUT
BUFFER
DAC
REGISTER
V
OUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SYNC SCLK DIN
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The
AD5300
is a single, 8-bit buffered voltage output DAC that
operates from a single 2.7 V to 5.5 V supply, consuming 115 μA
at 3 V. Its on-chip precision output amplifier allows rail-to-rail
output swing to be achieved. The AD5300 uses a versatile 3-wire
serial interface that operates at clock rates up to 30 MHz and is
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards.
The reference for the AD5300
1
is derived from the power supply
inputs and thus gives the widest dynamic output range. The part
incorporates a power-on reset circuit that ensures that the DAC
output powers up to 0 V and remains there until a valid write takes
place to the device. The part contains a power-down feature that
reduces the current consumption of the device to 200 nA at 5 V
and provides software selectable output loads while in power-
down mode. The part is put into power-down mode over the
serial interface.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 0.7 mW at 5 V, reducing to 1 μW in
power-down mode.
The AD5300 is one of a family of pin-compatible DACs. The
AD5310
is the 10-bit version, and the
AD5320
is the 12-bit
version. The AD5300/AD5310/AD5320 are available in 6-lead
SOT-23 packages and 8-lead MSOP packages.
PRODUCT HIGHLIGHTS
1.
2.
Available in 6-lead SOT-23 and 8-lead MSOP packages.
Low power, single-supply operation. This part operates from a
single 2.7 V to 5.5 V supply and typically consumes 0.35 mW
at 3 V and 0.7 mW at 5 V, making it ideal for battery-powered
applications.
The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a slew rate of 1 V/μs.
Reference derived from the power supply.
High speed serial interface with clock speeds up to 30 MHz.
Designed for very low power consumption. The interface
powers up only during a write cycle.
Power-down capability. When powered down, the DAC
typically consumes 50 nA at 3 V and 200 nA at 5 V.
3.
4.
5.
6.
1
Patent pending; protected by U.S. Patent No. 5684481.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.
00471-001
AD5300–SPECIFICATIONS
Parameter
STATIC PERFORMANCE
2
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
3
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Capacitive Load Stability
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short-Circuit Current
Power-Up Time
LOGIC INPUTS
3
Input Current
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INH
, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
I
DD
(All Power-Down Modes)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
POWER EFFICIENCY
I
OUT
/I
DD
8
(V
DD
= 2.7 V to 5.5 V; R
L
= 2 k to GND; C
L
= 500 pF to GND; all specifications
T
MIN
to T
MAX
, unless otherwise noted.)
Unit
Bits
LSB
LSB
LSB
LSB
% of FSR
µV/°C
ppm of FSR/°C
V
µs
V/µs
pF
pF
nV-s
nV-s
Ω
mA
mA
µs
µs
±
1
0.8
0.6
µA
V
V
V
V
pF
V
µA
µA
µA
µA
%
DAC Active and Excluding Load Current.
V
IH
= V
DD
and V
IL
= GND.
V
IH
= V
DD
and V
IL
= GND.
V
IH
= V
DD
and V
IL
= GND.
V
IH
= V
DD
and V
IL
= GND.
I
LOAD
= 2 mA. V
DD
= 5 V.
Conditions/Comments
B Version
1
Min
Typ
Max
+0.5
–0.5
–20
–5
0
4
1
470
1000
20
0.5
1
50
20
2.5
5
±
1
±
0.25
+3.5
–3.5
±
1.25
See Figure 2.
Guaranteed Monotonic by Design. See Figure 3.
All Zeros Loaded to DAC Register. See Figure 6.
All Ones Loaded to DAC Register. See Figure 6.
V
DD
6
1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex).
R
L
= 2 kΩ; 0 pF < C
L
< 500 pF. See Figure 16.
R
L
=
∞
.
R
L
= 2 kΩ.
1 LSB Change Around Major Carry. See Figure 19.
V
DD
= 5 V.
V
DD
= 3 V.
Coming Out of Power-Down Mode. V
DD
= 5 V.
Coming Out of Power-Down Mode. V
DD
= 3 V.
2.4
2.1
3
2.7
140
115
0.2
0.05
93
5.5
250
200
1
1
V
DD
= 5 V.
V
DD
= 3 V.
V
DD
= 5 V.
V
DD
= 3 V.
NOTES
1
Temperature range as follows: B Version: –40°C to +105°C.
2
Linearity calculated using a reduced code range of 4 to 251. Output unloaded.
3
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
–2–
REV.
D
AD5300
TIMING CHARACTERISTICS
1, 2
(V
Parameter
t
1 3
t
2
t
3
t
4
t
5
t
6
t
7
t
8
50
13
22.5
13
5
4.5
0
50
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC
to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to
SYNC
Rising Edge
Minimum
SYNC
High Time
Limit at T
MIN
, T
MAX
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
33
13
13
13
5
4.5
0
33
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
See Figure 1.
3
Maximum SCLK frequency is 30 MHz at V
DD
= 3.6 V to 5.5 V and 20 MHz at V
DD
= 2.7 V to 3.6 V.
Specifications subject to change without notice.
t
1
SCLK
t
8
t
4
SYNC
t
3
t
2
t
7
t
6
t
5
DIN
DB15
DB0
Figure 1. Serial Write Operation
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C, unless otherwise noted.)
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . . . 150°C
SOT-23 Package
Power Dissipation . . . . . . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 240°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
MSOP Package
Power Dissipation . . . . . . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV.
D
–3–
AD5300
PIN CONFIGURATIONS
SOT-23
V
OUT 1
GND
2
6
MSOP
SYNC
V
DD 1
NC
2
NC
3
8
GND
DIN
5
SCLK
TOP VIEW
V
DD 3
(Not to Scale)
4
DIN
AD5300
AD5300
7
TOP VIEW
6
SCLK
(Not to Scale)
5
SYNC
V
OUT 4
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
SOT-23 MSOP
Pin No. Pin No. Mnemonic
1
2
3
4
5
6
4
8
1
7
6
5
V
OUT
GND
V
DD
DIN
SCLK
SYNC
Function
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and V
DD
should be decoupled
to GND.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates up to 30 MHz.
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the
input data. When
SYNC
goes low, it enables the input shift register and data is transferred in on the
falling edges of the following clocks. The DAC is updated following the 16th clock cycle, unless
SYNC
is taken high before this edge, in which case the rising edge of
SYNC
acts as an interrupt and
the write sequence is ignored by the DAC.
No Connect.
NC
2, 3
NC
–4–
REV.
D
Embedded System
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