FPD750SOT89
CE Low-Noise
High-Linearity
Packaged
pHEMT
FPD750SOT89CE
LOW-NOISE HIGH-LINEARITY PACKAGED
pHEMT
Package Style: SOT89
Product Description
The FPD750SOT89CE is a packaged depletion mode AlGaAs/InGaAs pseudomor-
phic High Electron Mobility Transistor (pHEMT). It features a 0.25μmx1500μm
Schottky barrier gate, defined by high-resolution stepper-based photolithography.
The double recessed gate structure minimizes parasitics to optimize performance.
The epitaxial structure is designed for improved linearity over a range of bias condi-
tions and input power levels.
Features
25dBm Output Power (P1dB)
18dB Small-Signal Gain
(SSG)
0.6dB Noise Figure
39dBm OIP
3
55% Power-Added Efficiency
FPD750SOT89CE: RoHS
Compliant (Directive
2002/95/EC)
Optimum Technology
Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
InP HBT
RF MEMS
LDMOS
Applications
Drivers or Output Stages in
PCS/Cellular Base Station
Transmitter Amplifiers
High Intercept-point LNAs
WLL, WLAN, and Other Types
of Wireless Infrastructure
Systems.
Parameter
P
1dB
Gain Compression
Small-Signal Gain (SSG)
PAE
Noise Figure (NF)
OIP
3
Min.
23
16.5
Specification
Typ.
25
18
50
0.8
Max.
Unit
dBm
dB
%
dB
dB
dBm
dBm
Condition
V
DS
=5V, I
DS
=50% I
DSS
V
DS
=5V, I
DS
=50% I
DSS
V
DS
=5V, I
DS
=50% I
DSS
, P
OUT
=P
1dB
V
DS
=5V, I
DS
=50%
V
DS
=5V, I
DS
=25%
V
DS
=5V, I
DS
=50% I
DSS
. Matched for optimal
power.
Matched for best IP
3
V
DS
=1.3V, V
GS
=0V
V
DS
=1.3V, V
GS
≈+1V
V
DS
=1.3V, V
GS
=0V
V
GS
=-5V
V
DS
=1.3V, I
DS
=0.75mA
I
GS
=0.75mA
I
GD
=0.75mA
1.0
36
0.6
38
39
Saturated Drain-Source Current (I
DSS
)
Maximum Drain-Source Current
(I
MAX
)
Transconductance (GM)
Gate-Source Leakage Current (IGSO)
Pinch-Off Voltage (V
P
)
Gate-Source Breakdown Voltage
(V
BDGS
)
Gate-Drain Breakdown Voltage
(V
BDGD
)
185
230
375
200
280
mA
mA
ms
|0.7|
|12|
|12|
1
|1.0|
|16|
|16|
15
|1.3|
μA
V
V
V
Thermal Resistivity (θJC) *
83
°C/W
*Note: T
AMBIENT
=22°C, RF specifications measured at f=1850GHz using CW signal (except as noted).
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc.
DS100121
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
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FPD750SOT89CE
Absolute Maximum Ratings
1
Parameter
Drain-Source Voltage (V
DS
)
(-3V<V
GS
<0.5V)
Gate-Source Voltage (V
GS
)
(0V<V
DS
<+8V)
Drain-Source Current (I
DS
)
(For V
DS
>2V)
Gate Current (I
G
) (Forward or reverse)
RF Input Power (P
IN
)
2
(Under any acceptable bias state)
Channel Operating Temperature (T
CH
)
(Under any acceptable bias state)
Storage Temperature (T
STG
)
(Non-Operating Storage)
Total Power Dissipation (P
TOT
)
3, 4
Gain Compression
(Under bias conditions)
Simultaneous Combination of Limits
6
(2 or more max. limits)
Notes:
1
T
AMBIENT
=22°C unless otherwise noted; exceeding any one of these absolute max-
imum ratings may cause permanent damage to the device.
2
Max. RF input limit must be further limited if input VSWR>2.5:1.
3
Users should avoid exceeding 80% of 2 or more Limits simultaneously.
4
Total Power Dissipation (P
TOT
) defined as (P
DC
+P
IN
)–P
OUT
, where P
DC
: DC Bias
Power, P
IN
: RF Input Power, P
OUT
: RF Output Power.
Total Power Dissipation to be de-rated as follows above 22°C:
P
TOT
=1.8-(0.012W/°C)xT
PACK
, where T
PACK
=source tab lead temperature
above 22°C. (Coefficient of de-rating formula is Thermal Conductivity.)
Exampe: For a 65°C carrier temperature: P
TOT
=1.8W-(0.012x(65-22))=1.28W
Rating
8
-3
I
DSS
7.5
175
175
-55 to 150
1.8
5
Unit
V
V
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical perfor-
mance or functional operation of the device under Absolute Maximum Rating condi-
tions is not implied.
RoHS status based on EUDirective2002/95/EC (at time of this document revision).
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended appli-
cation circuitry and specifications at any time without prior notice.
mA
mW
°C
°C
W
dB
Biasing Guidelines
Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger num-
ber of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that gate bias is
applied before drain bias, otherwise the pHEMT may be induced to self-oscillate.
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode
devices.
For standard Class A operation, an operating point of 50% of I
DSS
is recommended. A small amount of RF gain expansion prior
to the onset of compression is normal for this operating point. A class A/B Bias of 25% to 33% of I
DSS
to achieve better OIP
3
and Noise Figure performance is suggested.
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DS100121
FPD750SOT89CE
Frequency Response
Biased @ 5V 50%IDSS
35
MSG
Biased @ 5V, 100mA
1.2
S21
30
25
20
15
10
No ise Fig ure (d B)
1
0.8
0.6
0.4
N.F. (dB)
0.2
Mag S21 &
MSG
5
0
0.9
1.3
1.7
2.1
2.5
2.9
3.7
4.1
4.5
4.9
5.3
0.5
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8
Frequency (GHz)
Freque n cy (GHz)
Note: Device tuned for minimum noise figure.
Temperature Response
B iased @ 5V,50%ID SS
D ata take n on Ev al Bo ard at 1.85GH z
Biased @ 5V, 33% IDSS
Data taken on Eval board @ 1.85GHz
20.0
19.0
SSG (dB)
18.0
17.0
16.0
15.0
14.0
-10
10
20
30
40
50
60
70
80
-20
90
0
T emperature (C )
SSG
(dB)
P1dB (dBm)
26.0
25.0
24.0
23.0
22.0
21.0
20.0
19.0
18.0
17.0
16.0
1.80
1.60
No ise Fig ure (d B)
P1dB (dBm )
1.40
1.20
1.00
0.80
0.60
0.40
0
10
20
30
40
50
60
70
80
-20
-10
Temperature (C)
N.F.
(dB)
3.3
0
5.7
Note: Data taken on evaluation board tuned for maximum power. Acheivable noise figure is lower when optimized.
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90
FPD750SOT89CE
Typical Tuned RF Performance
Power Transfer Characteristic
VDS = 5V I DS = 50% I DSS at
f
= 1. 85 GHz
26.0
3.50
25.5
Po ut (d B )
m
Com p Po int
60. 0%
60 .0%
PAE
E ff .
Drai n E ffi ciency and P AE
3.00
Gain Comp
ressio (dB)
n
2.50
2.00
1.50
1.00
0.50
20. 0%
50. 0%
25.0
Output Power (dBm)
50 .0%
D ra in Ef fic ien c y (%
24.5
24.0
23.5
23.0
22.5
22.0
4
5
6
7
8
Inp Po
ut wer (d
Bm)
9
10
11
12
PA E (% )
40. 0%
40 .0%
30. 0%
30 .0%
20 .0%
0.00
-0.50
10. 0%
1
3
5
7
In pu t Po we r (d B m )
9
11
10 .0%
Note: Typical power and efficiency is shown above. The devices were biased nominally
at V
DS
=5V, I
DS
=50% of I
DSS
, at a test frequency of 1.85GHz. The test devices were
tuned (input and output tuning) for maximum output power at 1dB gain compression.
Typical I nterm odulation Perform ance
V DS = 5V IDS = 50% I DS S at f = 1.85GHz
DC IV Curves FPD750SOT89
-23. 00
20
Pout ( dBm)
3rd s (d Bc)
0.30
0.25
3rd Order I M P roducts (dBc)
-28. 00
Drain-Sour ce C
urrent (A)
18
Output Power (dBm)
0.20
16
-33. 00
14
-38. 00
12
0.15
0.10
VG=-1.50
VG=-1.25V
VG=-1.00V
VG=-0.75V
VG=-0.50V
VG=-0.25V
VG=0V
0.05
10
-7.1
-6.0
-5 .0
-4. 0
-3. 0
-2.1
-1.0
0.0
1.0
1.9
I nput Power (dBm)
-43. 00
0.00
0.0
0.5
1. 0
1. 5
2. 0
2. 5
3. 0
3. 5
4. 0
4. 5
5.0
5.5
6.0
Drain-Source Voltage (V)
Note: pHEMT devices have enhanced intermodulation per-
formance. This yields OIP3 values of about
P1dB+14dBm.This IMD enhancement is affected by the
quiescent bias and the matching applied to the device.
Note: The recommended method for measuring I
DSS
, or
any particular I
DS
, is to set the Drain-Source voltage (V
DS
)
at 1.3V. This measurement point avoids the onset of spuri-
ous self-oscillation which would normally distort the cur-
rent measurement (this effect has been filtered from the I-
V curves presented above). Setting the V
DS
>1.3V will gen-
erally cause errors in the current measurements, even in
stabilized circuits.
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DS100121
FPD750SOT89CE
Typical Output Plane Power Contours
(V
DS
=5V, I
DS
=50% I
DSS
)
FPD750SOT89 POWER CONTUORS 900MHz
1.0
0 .6
Swp Max
151
2.0
0.8
10.0
3 .0
0. 4
0.2
0.6
0.8
1.0
2.0
4.0
5.0
0
20dBm
21dBm
-3
.0
.4
-0
23dBm
22dBm
-0.
6
0
-2.
Swp Min
1
-0.8
1850 MHz
Contours swept with a constant input power, set so that optimum P1dB is
achieved at the point of output match.
Input (Source plane)
Γs:
0.50∠142.8º
0.37+j0.35 (normalized)
18.5-j17.5Ω
Nominal IP3 performance is obtained with this input plane match, and
the output plane match as shown.
900 MHz
Contours swept with a constant input power, set so that optimum P1dB is
achieved at the point of output match.
Input (Source plane)
Γs:
0.79∠36.9º
1.0+j2.6 (normalized)
50+j130Ω
Nominal IP3 performance is obtained with this input plane match, and
the output plane match as shown.
Typical Scattering Parameters
(50Ω System)
FPD750SOT8 9 5V / 50%IDSS
1.0
6
0.
FPD750SOT8 9 5V / 5 0%IDSS
1.0
6
0.
-1.0
Swp Max
8GHz
0.8
0 .8
4 GHz
3.5 GHz
3 GHz
0 .2
3
7 GHz
.0
1 0. 0
10.0
2.0
0.2
0.6
0.8
1.0
2.0
3.0
4.0
5.0
0.4
0
2.5 GHz
- 10 . 0
0
4 GHz
3 GHz
2 GH z
.0
- 0.
2
-1 0. 0
.
-0
.0
-2
-0
.6
- 0 .8
- 0. 8
-1.0
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-1.0
S11
1 GHz
Swp Min
0.5GHz
S22
-0
.
.0
-2
6
S wp Min
0.5GHz
-
.4
-0
1.5 GHz
4
-5
-4
.0
3.
0
- 5.
0
- 0.
2
2 GHz
.0
1 G Hz
4.0
5.0
0.2
0.4
0.6
0.8
1.0
3.0
10.0
0 .2
0
4.
5 .0
0.
4
5 GHz
0.
4
6 GHz
2.
0
2.
0
6 GHz
5 GHz
7 G Hz
-4
.
0
24dBm
-5 .0
-0.2
-10.0
0.
4
3.
0
4 .0
5.0
0.2
10.0
19dBm
25dBm
S wp Max
8GHz
3.
0
0
4.
0
5.
10 .0
-4
.0
-3
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