DS1248 datasheet, PDF - EEWORLD Datasheet

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DS1248: Description1024k NV SRAM with Phantom Clock; File Size283KB，21 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

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DS1248 Overview

1024k NV SRAM with Phantom Clock

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DS1248/DS1248P

1024k NV SRAM with Phantom Clock

www.maxim-ic.com

FEATURES

Real-time clock (RTC) keeps track of

hundredths of seconds, minutes, hours, days,

date of the month, months, and years

128k x 8 NV SRAM directly replaces

volatile static RAM or EEPROM

Embedded lithium energy cell maintains

calendar operation and retains RAM data

Watch function is transparent to RAM

operation

Month and year determine the number of

days in each month; valid up to 2100

Full 10% operating range

Operating temperature range: 0°C to +70°C

Over 10 years of data retention in the

absence of power

Lithium energy source is electrically

disconnected to retain freshness until power

is applied for the first time

DIP Module only

Standard 32-pin JEDEC pinout

PowerCap

Module Board only

Surface mountable package for direct

connection to PowerCap containing

battery and crystal

Replaceable battery (PowerCap)

Pin for pin compatible with DS1244P

and DS1251P

PIN ASSIGNMENT

RST

A16

A14

A12

DQ0

DQ1

DQ2

GND

A15

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

32-Pin Encapsulated Package

740mil Flush

RST

A15

A16

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

GND V

BAT

A14

A13

A12

A11

A10

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

PowerCap is a registered trademark of Dallas Semiconductor.

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112801

DS1248/DS1248P

the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the

and

control of the SmartWatch. These 64 write cycles are used only to gain access to the

phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write

cycles generated to gain access to the phantom clock are also writing data to a location in the mated

RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a

phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit

comparison register. If a match is found, the pointer increments to the next location of the comparison

subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the

present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for

a total of 64 write cycles as described above until all the bits in the comparison register have been

matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or

from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either

receive or transmit data on DQ0, depending on the level of the

pin or the

pin. Cycles to other

locations outside the memory block can be interleaved with

cycles without interrupting the pattern

recognition sequence or data transfer sequence to the phantom clock.

PHANTOM CLOCK REGISTER INFORMATION

The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially

accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating

the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading

individual bits within a register could produce erroneous results. These read/write registers are defined in

Figure 2.

Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and

writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of

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DS1248 Related Products

	DS1248	DS1248P	DS1248WP120IND	DS1248Y70IND	DS1248YP70IND
Description	1024k NV SRAM with Phantom Clock	1024k NV SRAM with Phantom Clock	1024k NV SRAM with Phantom Clock	1024k NV SRAM with Phantom Clock	1024k NV SRAM with Phantom Clock

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