P4C187/P4C187L
ULTRA HIGH SPEED 64K x 1
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45 ns (Commercial)
– 12/15/20/25/35 /45 ns (Industrial)
– 15/20/25/35/45/55/70/85 ns (Military)
Low Power Operation
– 743 mW Active -10
– 660/770 mW Active for -12/15
– 550/660 mW Active for -20/25/35
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C187
– 5.5 mW Standby (CMOS Input) P4C187L (Military)
Single 5V±10% Power Supply
Data Retention with 2.0V Supply (P4C187L
Military)
Separate Data I/O
Three-State Output
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290x490 mil LCC
– 28-Pin 350x550 mil LCC
DESCRIPTION
The P4C187/P4C187L are 65, 536-bit ultra high speed
static RAMs organized as 64K x 1. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. The RAMs operate from a single 5V ± 10%
tolerance power supply. Data integrity is maintained for sup-
ply voltages down to 2.0V, typically drawing 10µA.
Access times as fast as 10 nanoseconds are available,
greatly enhancing system speeds. CMOS reduces power
consumption to a low 743mW active, 193/83mW standby
for TTL/CMOS inputs and only 5.5 mW standby for the
P4C187L.
The P4C187/P4C187L are available in 22-pin 300 mil DIP,
24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-
viding excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P3, D3, C3)
SOJ (J4)
LCC Pin configurations at end of datasheet.
Document #
SRAM111
REV B
1
Revised April 2007
P4C187/187L
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Military
Ambient
Temperature
GND
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions Typ. Unit
V
IN
= 0V
V
OUT
= 0V
5
7
pF
pF
–55°C to +125°C
–40°C to +85°C
Industrial
0°C to +70°C
Commercial
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage V
CC
= Min., I
IN
= 18 mA
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
,
V
OUT
= GND to V
CC
Mil.
Com’l.
Mil.
Com’l.
2.4
–10
–5
–10
–5
___
___
___
___
+10
+5
+10
+5
40
35
20
15
Test Conditions
P4C187
Min
Max
2.2
V
CC
+0.5
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
2.4
–5
n/a
–5
n/a
___
___
___
___
+5
n/a
+5
n/a
40
n/a
1.0
n/a
P4C187L
Unit
Min
Max
2.2
V
CC
+0.5 V
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
V
V
V
V
V
V
µA
µA
mA
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
Standby Power Supply
CE
≥
V
IH
Mil.
Current (TTL Input Levels) V
CC
= Max .,
Ind./Com’l.
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
≥
V
HC
Mil.
V
CC
= Max.,
Ind./Com’l.
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
I
SB1
mA
n/a = Not Applicable
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM111
REV B
Page 2 of 12
P4C187/187L
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter
Dynamic
Operating
Current*
Temperature
Range
Commercial
Industrial
Military
–10
180
N/A
N/A
–12
170
180
N/A
–15
160
170
170
–20
155
160
160
–25
150
155
155
–35
N/A
150
150
–45
N/A
N/A
145
–55
N/A
N/A
145
–70
N/A
N/A
145
–85 Unit
N/A
N/A
145
mA
mA
mA
I
CC
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
.
DATA RETENTION CHARACTERISTICS (P4C187L Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R†
*T
A
= +25°C
§t
RC
= Read Cycle Time
†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Conditons
Min
2.0
Typ.*
V
CC
=
2.0V
3.0V
Max
V
CC
=
2.0V
3.0V
Unit
V
CE
≥
V
CC
–0.2V,
V
IN
≥
V
CC
–0.2V
or V
IN
≤
0.2V
0
t
RC§
10
15
600
900
µA
ns
ns
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document #
SRAM111
REV B
Page 3 of 12
P4C187/187L
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol Parameter
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
PU
t
PD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
0
10
2
2
5
0
12
-10
-12
-15
-20
-25
-35
-45
-55
-70
-85
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
10
10
2
2
6
0
15
12
12
12
2
2
8
0
20
15
15
15
2
2
10
0
25
20
20
20
2
2
12
0
35
25
25
25
2
2
17
0
45
35
35
35
2
2
20
0
55
45
45
45
2
2
25
0
70
55
55
65
2
2
30
0
85
70
70
70
2
2
35
85
85
85
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
Notes:
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM111
REV B
Page 4 of 12
P4C187/187L
AC CHARACTERISTICS - WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol Parameter
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Write Cycle Time
Chip Enable Time to
End of Write
Address Valid to End
of Write
Address Set-up Time
Write Pulse Width
Address Hold Time
from End of Write
Data Valid to End of
Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
-10
-12
-15
-20
-25
-35
-45
-55
-70
-85
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
8
8
0
8
0
6
0
6
0
0
12
10
10
0
10
0
7
0
7
0
15
12
12
0
12
0
10
0
8
0
20
15
15
0
15
0
13
0
12
0
25
20
20
0
20
0
15
0
15
0
35
25
25
0
25
0
20
0
17
0
45
30
30
0
30
0
25
0
20
0
55
35
35
0
35
0
30
0
25
0
70
40
40
0
40
0
35
0
30
0
85
45
45
0
45
0
40
0
35
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(9)
WE
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
Document #
SRAM111
REV B
Page 5 of 12
Embedded System
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