P4C164-12DWMBLF datasheet, PDF

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P4C164-12DWMBLF: DescriptionULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS; Categorystorage storage; File Size184KB，16 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/; Environmental Compliance

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P4C164-12DWMBLF Overview

ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS

P4C164-12DWMBLF Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Pyramid Semiconductor Corporation
Parts packaging code	DIP
package instruction	DIP, DIP28,.6
Contacts	28
Reach Compliance Code	compli
ECCN code	3A001.A.2.C
Maximum access time	12 ns
I/O type	COMMON
JESD-30 code	R-CDIP-T28
memory density	65536 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	28
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	8KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP28,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum seat height	5.08 mm
Maximum standby current	0.025 A
Minimum standby current	4.5 V
Maximum slew rate	0.18 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

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P4C164

ULTRA HIGH SPEED 8K x 8

STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 8/10/12/15/20/25/35/70/100 ns (Commercial)

– 10/12/15/20/25/35/70/100 ns(Industrial)

– 12/15/20/25/35/45/70/100 ns (Military)

Low Power Operation

Output Enable and Dual Chip Enable Control

Functions

Single 5V±10% Power Supply

Data Retention with 2.0V Supply, 10 µA Typical

Current (P4C164L Military)

Common Data I/O

Fully TTL Compatible Inputs and Outputs

Standard Pinout (JEDEC Approved)

– 28-Pin 300 mil Plastic DIP, SOJ

– 28-Pin 600 mil Plastic DIP (70 & 100ns)

– 28-Pin 300 mil SOP (70 & 100ns)

– 28-Pin 300 mil Ceramic DIP

– 28-Pin 600 mil Ceramic DIP

– 28-Pin 350 x 550 mil LCC

– 32-Pin 450 x 550 mil LCC

– 28-Pin CERPACK

DESCRIPTION

The P4C164 is a 65,536-bit ultra high-speed static RAM

organized as 8K x 8. The CMOS memory requires no

clocks or refreshing and has equal access and cycle

times. Inputs are fully TTL-compatible. The RAM operates

from a single 5V±10% tolerance power supply. With

battery backup, data integrity is maintained with supply

voltages down to 2.0V. Current drain is typically 10 µA

from a 2.0V supply.

Access times as fast as 8 nanoseconds are available,

permitting greatly enhanced system operating speeds.

The P4C164 is available in 28-pin 300 mil DIP and SOJ, 28-

pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil

LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK.

The 70ns and 100ns P4C164s are available in the 600 mil

plastic DIP.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP (P5, P6, C5, C5-1, D5-1, D5-2),

SOJ (J5), CERPACK (F4), SOP(S6)

SEE PAGE 7 FOR LCC PIN CONFIGURATIONS

1519B

Document #

SRAM115

REV F

Revised June 2007

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