P4C150
ULTRA HIGH SPEED 1K X 4
RESETTABLE STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 15/20/25/35 ns (Military)
Chip Clear Function
Low Power Operation
Single 5V ± 10% Power Supply
Separate Input and Output Ports
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP
– 24-Pin 300 mil SOIC
– 28-Pin LCC (350 x 550 mils)
– 24-Pin CERPACK
DESCRIPTION
The P4C150 is a 4,096-bit ultra high-speed static RAM
organized as 1K x 4 for high speed cache applications.
The RAM features a reset control to enable clearing all
words to zero within two cycle times. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs and outputs are fully TTL-
compatible. The RAM operates from a single 5V ± 10%
tolerance power supply.
Access times as fast as 10 nanoseconds are available
permitting greatly enhanced system operating speeds.
Time required to reset is only 20 ns for the 10 ns SRAM.
CMOS is used to reduce power consumption to a low
level.
The P4C150 is available in 24-pin 300 mil DIP and SOIC
packages providing excellent board level densities.
The device is also available in a 28-pin LCC package as
well as a 24-pin FLATPACK for military applications.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P4, C4, D4), SOIC (S4)
CERPACK (F3) SIMILAR
LCC (L5)
Document #
SRAM105
REV A
1
Revised October 2005
P4C150
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
– 0.5 to +7
– 0.5 to
V
CC
+0.5
– 55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
– 55 to +125
– 65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
CONDITIONS
Grade
(2)
Commercial
Military
Ambient Temp
0°C to 70°C
-55°C to +125°C
Gnd
0V
0V
V
CC
5.0V
± 10%
5.0V
± 10%
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
5
7
pF
pF
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output High Voltage
(TTL Load)
Output Low Voltage
(TTL Load)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
Test Conditions
I
OH
= –4 mA, V
CC
= Min.
I
OL
= +8 mA, V
CC
= Min
2.2
–0.5
(3)
–5
–5
P4C150
Min.
2.4
0.4
V
CC
=+0.5
0.8
+5
+5
Max.
Unit
V
V
V
V
µA
µA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current
Temperature
Range
Commercial
Military
-10
130
N/A
-12
130
N/A
-15
120
145
-20
115
135
-25
100
125
-35
N/A
120
Unit
mA
mA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to MAXIMUM rating condi-
tions for extended periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than – 3.0V and
– 100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM105
REV A
Page 2 of 11
P4C150
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable to
Data Valid
Output Enable to
Output in Low Z
Output Disable to
Output in High Z
-10
10
10
8
2
2
4
7
2
5
2
2
2
12
-12
15
12
10
2
2
6
9
2
7
-15
20
15
12
2
2
8
10
2
9
-20
-25
25
20
14
2
2
10
14
2
11
13
13
15
2
25
15
2
2
35
-35
Min Max Min Max Min Max Min Max Min Max Min Max
35
35
Unit
ns
ns
ns
ns
ns
15
20
ns
ns
ns
16
ns
TIMING WAVEFORM OF READ CYCLE NO. 1
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 2 (CS CONTROLLED)
(5, 7)
CS
Notes:
5.WE is HIGH for READ cycle.
6.CS and
OE
are LOW for READ cycle.
7.ADDRESS must be valid prior to, or concident with,
CS
transition
LOW, t
AA
must still be met.
8. Transition is measured ±200 mV from steady state voltage
prior to change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address to
the first transitioning address.
Document #
SRAM105
REV A
Page 3 of 11
P4C150
TIMING WAVEFORM OF READ CYCLE NO. 3 (OE Controlled)
(5)
OE
AC CHARACTERISTICS—RESET CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol
t
RRC
t
WER
t
CR
t
RP
t
HCR
t
HWR
t
RLZ
t
RHZ
Parameter
Reset Cycle Time
Write Enable High to
Beginning of Reset
Chip Select Low to
Beginning of Reset
Reset Pulse Width
Chip Select Hold
after End of Reset
Write Enable Hold
after End of Reset
Reset High to
Output in Low Z
Reset Low to
Output in High Z
-10
Min Max
20
0
0
10
0
10
0
0
8
-12
Min Max
24
0
0
12
0
12
0
0
10
-15
Min Max
30
0
0
15
0
15
0
0
12
-20
Min Max
40
0
0
20
0
20
0
0
16
-25
Min Max
50
0
0
25
0
25
0
0
20
-35
Min Max
70
0
0
30
0
35
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF RESET CYCLE
Document #
SRAM105
REV A
Page 4 of 11
P4C150
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time from
End of Write
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
-10
-25
-12
-15
-20
-35
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
10
8
8
0
8
0
5
0
5
2
2
12
10
10
1
10
1
8
1
8
2
15
11
13
1
11
1
11
1
12
3
20
13
16
1
13
1
13
1
15
3
25
15
20
2
15
2
15
2
20
3
35
20
25
2
20
2
20
2
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(10)
WE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED)
(10)
CS
Notes:
10.
CS
and
WE
must be LOW for WRITE cycle.
11. If
CS
goes HIGH simultaneously with
WE
high, the output remains
in a high impedance state.
12. Write Cycle Time is measured from the last valid address to the first
transition address.
Document #
SRAM105
REV A
Page 5 of 11
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