P4C1298/P4C1298L
ULTRA HIGH SPEED 64K x 4
STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25/35 ns (Commercial/Industrial)
– 15/20/25/35/45 ns (Military)
Low Power
Single 5V±10% Power Supply
Output Enable & Chip Enable control functions
Data Retention with 2.0V Supply
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350x550 mil LCC
DESCRIPTION
The P4C1298/L are a 262,144-bit ultra high speed static RAM
organized as 64K x 4. The CMOS memory requires no clock
or refreshing and has equal access and cycle times. Inputs
and outputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply. With battery
backup, data integrity is maintained for supply voltages down
to 2.0V. Current drain is typically 10 µA from a 2.0V supply.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
The P4C1298 is available in a 28-pin 300 mil DIP or SOJ, as
well as a 28-pin 350x500 mil LCC package, providing
excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P5, C5)
SOJ (J5)
LCC (L5)
Document #
SRAM135
REV OR
Revised April 2007
1
P4C1298/L
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
V
°C
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Military
Industrial
Commercial
Ambient
Temperature
-55°C to +125°C
–40°C to +85°C
0°C to +70°C
GND
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions Typ. Unit
V
IN
= 0V
V
OUT
= 0V
5
7
pF
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
I
SB1
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
V
CC
= Min., I
IN
= 18 mA
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
V
OUT
= GND to V
CC
CE
≥
V
IH
V
CC
= Max ., f = Max., Outputs
Open
CE
≥
V
HC
V
CC
= Max., f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
Mil
Ind/Comm
Mil
Ind/Comm
2.4
Test Conditions
P4C1298
Min
Max
2.2
–0.5
(3)
V
CC
–0.2
–0.5
(3)
V
CC
+0.5
0.8
P4C1298L
Min
Max
2.2
–0.5
(3)
V
CC
+0.5
0.8
V
CC
+0.5
0.2
–1.2
0.4
2.4
Unit
V
V
V
V
V
V
V
V
CC
+0.5 V
CC
–0.2
0.2
–1.2
0.4
–0.5
(3)
–5
+5
–10
+10
µA
Output Leakage Current
Standby Power Supply
Current (TTL Input Levels)
Standby Power Supply
Current
(CMOS Input Levels)
–5
___
___
+5
40
20
10
10
–10
___
___
___
___
+10
20
N/A
10
N/A
µA
mA
mA
mA
mA
___
___
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM135
REV OR
Page 2 of 11
P4C1298/L
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
Industrial
Military
–15
160
160
160
–20
125
135
150
–25
115
120
120
–35
110
115
120
Unit
mA
mA
mA
I
CC
Dynamic Operating Current*
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
DATA RETENTION CHARACTERISTICS (P4C1298L ONLY)
Symbol
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
CE
≥
V
CC
–0.2V,
V
IN
≥
V
CC
–0.2V or
V
IN
≤
0.2V
Test Conditions
Min
2.0
10
0
t
RC§
15
1000
2000
Typ.*
V
CC
=
2.0V
3.0V
Max
V
CC
=
2.0V 3.0V
Unit
V
µA
ns
ns
*T
A
= +25°C
§
†
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document #
SRAM135
REV OR
Page 3 of 11
P4C1298/L
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
0
0
3
3
15
-15
Min
-20
-25
Min
25
20
20
25
25
3
3
10
10
15
15
0
9
15
0
20
25
0
0
3
3
-35
Max Min
35
35
35
3
3
15
25
0
20
0
35
Max
-45
Min
45
45
45
Max
Unit
ns
ns
ns
ns
ns
20
30
20
45
ns
ns
ns
ns
ns
ns
Max Min Max
20
15
15
3
3
8
8
0
9
0
15
OE
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
Document #
SRAM135
REV OR
Page 4 of 11
P4C1298/L
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)
(5,6)
CE
Notes:
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM135
REV OR
Page 5 of 11
京公网安备 11010802033920号
EEWORLD
